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jeevanreddymandali
Adventurer
Adventurer
13,320 Views
Registered: ‎11-03-2013

No output from FIFO

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Hi guys, I am not getting the output from FIFO to which a simple counter is the input. Please check my code and tell me what wrong am I doing. My idea is when source is ready to give, destination will read so, I gave it to rd_en and at the end dst_rdy to src_rdy(the dependency). No output is on tx_d_i.

Inst_FIFO: FIFO PORT MAP(
		rst => reset_i,
		wr_clk => s_wren,
		rd_clk => user_clk_i,
		din => sdin,
		wr_en => '1',
		rd_en => not(tx_src_rdy_n_i),
		dout => tx_d_i,
		full => open,
		empty => open
	);
	tx_src_rdy_n_i <= tx_dst_rdy_n_i;

 Regards,

jeevanreddymandali
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vsrunga
Xilinx Employee
Xilinx Employee
21,083 Views
Registered: ‎07-11-2011

Hi,

 

Can't guess anthing from your snashots.

The issue is with FIFO IP or you r over all design ?

If you suspect FIFO use it in standalone and check if your logic works.

I see wr_en is tied to '1' which should be controllled with fifo_full fllag.

If you can't simulate, the proper way to debug this is insert chipscope and capture reset, wr_enm d_en , full, empyty din , clk and dout and see which signal is stuck to have more clues.

 

Regards,

Vanitha.

 

 

 

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5 Replies
vsrunga
Xilinx Employee
Xilinx Employee
13,315 Views
Registered: ‎07-11-2011

Hi,

 

FIFO needs free running clocks, it looks you have given enable as clock, can you show your RTL too?

Can you see empty goes low ?

It indicates that data is written into FIFO, I would suggest you to simulate your core first so as know whnat went wrong

Is reset assrted properly ?

 

 

Regards,

Vanitha.

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vsrunga
Xilinx Employee
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13,308 Views
Registered: ‎07-11-2011

Hi,

 

In addition,  I believe you have to assert write and read enabled by considering FIFO full and empty signals else the data may overflow.

 

fifo_wr_en <= '1' when full = '0'  else '0';

fifo_rd_en <= '1' when empty = '0' else  '0';

 

Please refer PG057for full details

http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v11_0/pg057-fifo-generator.pdf

 

Hope this clarifies.

 

 

Regards,

Vanitha.

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jeevanreddymandali
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Registered: ‎11-03-2013

Hi, I am not considering any fifo full, empty flags. Please tell me if I have to consider full, empty even in this case? Thanks for your time and here is my RTL. I cannot get a correct shot of it. Please try this.

fifo_1.jpgfifo_2.jpgfifo_3.jpg

Regards,

jeevanreddymandali
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vsrunga
Xilinx Employee
Xilinx Employee
21,084 Views
Registered: ‎07-11-2011

Hi,

 

Can't guess anthing from your snashots.

The issue is with FIFO IP or you r over all design ?

If you suspect FIFO use it in standalone and check if your logic works.

I see wr_en is tied to '1' which should be controllled with fifo_full fllag.

If you can't simulate, the proper way to debug this is insert chipscope and capture reset, wr_enm d_en , full, empyty din , clk and dout and see which signal is stuck to have more clues.

 

Regards,

Vanitha.

 

 

 

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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balkris
Xilinx Employee
Xilinx Employee
12,990 Views
Registered: ‎08-01-2008
Is this your own FIFO or you are using Xilinx FIFO generator core.
Xilinx FIFO generator core provide example design.

You can use the example design and simulate the core behavior
Thanks and Regards
Balkrishan
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