12-05-2013 10:20 PM
Hi guys, I am not getting the output from FIFO to which a simple counter is the input. Please check my code and tell me what wrong am I doing. My idea is when source is ready to give, destination will read so, I gave it to rd_en and at the end dst_rdy to src_rdy(the dependency). No output is on tx_d_i.
Inst_FIFO: FIFO PORT MAP( rst => reset_i, wr_clk => s_wren, rd_clk => user_clk_i, din => sdin, wr_en => '1', rd_en => not(tx_src_rdy_n_i), dout => tx_d_i, full => open, empty => open ); tx_src_rdy_n_i <= tx_dst_rdy_n_i;
Regards,
12-05-2013 11:08 PM
Hi,
Can't guess anthing from your snashots.
The issue is with FIFO IP or you r over all design ?
If you suspect FIFO use it in standalone and check if your logic works.
I see wr_en is tied to '1' which should be controllled with fifo_full fllag.
If you can't simulate, the proper way to debug this is insert chipscope and capture reset, wr_enm d_en , full, empyty din , clk and dout and see which signal is stuck to have more clues.
Regards,
Vanitha.
12-05-2013 10:23 PM - edited 12-05-2013 10:26 PM
Hi,
FIFO needs free running clocks, it looks you have given enable as clock, can you show your RTL too?
Can you see empty goes low ?
It indicates that data is written into FIFO, I would suggest you to simulate your core first so as know whnat went wrong
Is reset assrted properly ?
Regards,
Vanitha.
12-05-2013 10:34 PM
Hi,
In addition, I believe you have to assert write and read enabled by considering FIFO full and empty signals else the data may overflow.
fifo_wr_en <= '1' when full = '0' else '0';
fifo_rd_en <= '1' when empty = '0' else '0';
Please refer PG057for full details
Hope this clarifies.
Regards,
Vanitha.
12-05-2013 10:57 PM
Hi, I am not considering any fifo full, empty flags. Please tell me if I have to consider full, empty even in this case? Thanks for your time and here is my RTL. I cannot get a correct shot of it. Please try this.
Regards,
12-05-2013 11:08 PM
Hi,
Can't guess anthing from your snashots.
The issue is with FIFO IP or you r over all design ?
If you suspect FIFO use it in standalone and check if your logic works.
I see wr_en is tied to '1' which should be controllled with fifo_full fllag.
If you can't simulate, the proper way to debug this is insert chipscope and capture reset, wr_enm d_en , full, empyty din , clk and dout and see which signal is stuck to have more clues.
Regards,
Vanitha.
03-18-2014 03:49 AM