08-14-2018 05:03 AM
Hi,
I'm working on an application where I have a 96-bit word coming in from a bank of ADC, and I want to stream this through a 128-bit PCIe 2.0/3.0 xdma (integrated IP) interface.
If I just shove the 96-bits into a FIFO buffer and then into the xdma streaming port, I essentially "waste" 32 bits of bandwidth on the PCIe bus and downstream buffer space.
Would a reasonable approach be to use TWO back-to back asymmetric FIFOs, one 96:384 bits, and the other 384:128 (with commensurate clock division between) to pack the data?
Is there a better way?
Thanks,
-darin
08-14-2018 08:18 PM
Why not just pack the data in RTL? To do this you only 96 bits of storage and a simple state machine.
As each 96 bit value comes in you concatenate it with whatever remainder you have from the last clock cycle. If the total number of bits is >= 128 you push it into your FIFO. So, for example
Bits held + bits added - bits sent out = new bits held
0 96 0 96 (no word pushed)
96 96 128 64 (word pushed)
64 96 128 32 (word pushed)
32 96 128 0 (word pushed)
0 96 0 96 (no word pushed)
...
Avrum
08-17-2018 05:57 AM
I support the method described by avrum.
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