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surajit_sarkar
Observer
Observer
220 Views
Registered: ‎02-23-2021

Not getting output by using run post synthesis simulation for zcu104

any one help me please, Actually I am using zcu104 evaluation kit . I want to work on image processing . I used model composer and select Ip cataloge for code generation . Actuatty I followed below lectures 

Getting Started with the Avnet Ultra96, Part 1: Set Up the
Getting Started with the Avnet Ultra96, Part 2: Simulate Using Model Composer
Getting Started with the Avnet Ultra96, Part 3: Import IP and Validate the Design Using Vivado
https://in.mathworks.com/videos/part-4-program-the-design-onto-an-fpga-using-vivado-1559821264895.html

I used zcu104 in place of Avnet Ultra96 and followed copy . But even generate bit stream also success.

I am not getting output by using run post synthesis simulation using vivado (2020.1) means it is not working . I have used model composer and used same example (Color detection) .

I have used by default Input and output port and also by default I/O interface . 

I think it is not taking image from input .

so please me ...

My xdc file show ..

set_property IOSTANDARD LVCMOS18 [get_ports B_V_tready]
set_property IOSTANDARD LVCMOS18 [get_ports B_V_tvalid]
set_property IOSTANDARD LVCMOS18 [get_ports G_V_tready]
set_property IOSTANDARD LVCMOS18 [get_ports G_V_tvalid]
set_property IOSTANDARD LVCMOS18 [get_ports Out2_V_tready]
set_property IOSTANDARD LVCMOS18 [get_ports Out2_V_tvalid]
set_property IOSTANDARD LVCMOS18 [get_ports R_V_tready]
set_property IOSTANDARD LVCMOS18 [get_ports R_V_tvalid]
set_property IOSTANDARD LVCMOS18 [get_ports ap_clk]
set_property IOSTANDARD LVCMOS18 [get_ports ap_ctrl_done]
set_property IOSTANDARD LVCMOS18 [get_ports ap_ctrl_idle]
set_property IOSTANDARD LVCMOS18 [get_ports ap_ctrl_ready]
set_property IOSTANDARD LVCMOS18 [get_ports ap_ctrl_start]
set_property IOSTANDARD LVCMOS18 [get_ports ap_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {R_V_tdata[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Out2_V_tdata[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {B_V_tdata[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {G_V_tdata[5]}]

set_property PACKAGE_PIN E3 [get_ports G_V_tready]
set_property PACKAGE_PIN C2 [get_ports B_V_tready]
set_property PACKAGE_PIN N12 [get_ports {Out2_V_tdata[7]}]
set_property PACKAGE_PIN P12 [get_ports {Out2_V_tdata[6]}]
set_property PACKAGE_PIN N8 [get_ports {Out2_V_tdata[5]}]
set_property PACKAGE_PIN G6 [get_ports {B_V_tdata[5]}]
set_property PACKAGE_PIN F4 [get_ports {R_V_tdata[7]}]
set_property PACKAGE_PIN G7 [get_ports {B_V_tdata[3]}]
set_property PACKAGE_PIN N9 [get_ports {Out2_V_tdata[4]}]
set_property PACKAGE_PIN K9 [get_ports {G_V_tdata[0]}]
set_property PACKAGE_PIN J6 [get_ports {B_V_tdata[7]}]
set_property PACKAGE_PIN H6 [get_ports {B_V_tdata[4]}]
set_property PACKAGE_PIN K8 [get_ports {G_V_tdata[3]}]
set_property PACKAGE_PIN A5 [get_ports {R_V_tdata[5]}]
set_property PACKAGE_PIN M12 [get_ports {Out2_V_tdata[3]}]
set_property PACKAGE_PIN L10 [get_ports {G_V_tdata[5]}]
set_property PACKAGE_PIN N13 [get_ports {Out2_V_tdata[2]}]
set_property PACKAGE_PIN M11 [get_ports {Out2_V_tdata[1]}]
set_property PACKAGE_PIN N11 [get_ports {Out2_V_tdata[0]}]
set_property PACKAGE_PIN F6 [get_ports {R_V_tdata[0]}]
set_property PACKAGE_PIN L8 [get_ports {G_V_tdata[2]}]
set_property PACKAGE_PIN E5 [get_ports {R_V_tdata[1]}]
set_property PACKAGE_PIN D5 [get_ports {R_V_tdata[3]}]
set_property PACKAGE_PIN D6 [get_ports {R_V_tdata[2]}]
set_property PACKAGE_PIN G8 [get_ports {B_V_tdata[1]}]
set_property PACKAGE_PIN H8 [get_ports {B_V_tdata[0]}]
set_property PACKAGE_PIN H7 [get_ports {B_V_tdata[2]}]
set_property PACKAGE_PIN M8 [get_ports {G_V_tdata[7]}]
set_property PACKAGE_PIN J7 [get_ports {B_V_tdata[6]}]
set_property PACKAGE_PIN J9 [get_ports {G_V_tdata[1]}]
set_property PACKAGE_PIN F5 [get_ports {R_V_tdata[6]}]
set_property PACKAGE_PIN M9 [get_ports {G_V_tdata[6]}]
set_property PACKAGE_PIN B5 [get_ports {R_V_tdata[4]}]
set_property PACKAGE_PIN M10 [get_ports {G_V_tdata[4]}]
set_property PACKAGE_PIN A2 [get_ports ap_ctrl_done]
set_property PACKAGE_PIN C3 [get_ports ap_clk]
set_property PACKAGE_PIN D2 [get_ports ap_rst_n]
set_property PACKAGE_PIN C4 [get_ports Out2_V_tready]
set_property PACKAGE_PIN C1 [get_ports ap_ctrl_idle]
set_property PACKAGE_PIN D4 [get_ports G_V_tvalid]
set_property PACKAGE_PIN A3 [get_ports R_V_tready]
set_property PACKAGE_PIN E2 [get_ports Out2_V_tvalid]
set_property PACKAGE_PIN B1 [get_ports ap_ctrl_ready]
set_property PACKAGE_PIN B3 [get_ports ap_ctrl_start]
set_property PACKAGE_PIN E4 [get_ports B_V_tvalid]
set_property PACKAGE_PIN B4 [get_ports R_V_tvalid]

 

please help me anyone How i will get output from automated generate code (using model composer) and used that 

code in vivado and finally I will get output from vivado..

see the attachments.

 

 

1.png
2.png
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3 Replies
surajit_sarkar
Observer
Observer
129 Views
Registered: ‎02-23-2021

please somebody help me. I am not getting output from zcu104 evaluation  board by using system generator or model composer generated code.

plase show me or help me .

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watari
Teacher
Teacher
125 Views
Registered: ‎06-16-2013

Hi @surajit_sarkar 

 

Why don't you implement DUT ?

Also, this document is helpful for you.

Would you refer it ?

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v3_0/pg125-axi-traffic-gen.pdf

 

Best regards,

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surajit_sarkar
Observer
Observer
121 Views
Registered: ‎02-23-2021

 

Thankyou sir for your response . I am trying to implement DUT and following your refer link sir..

 

 

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