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vishalbk
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Registered: ‎03-21-2020

PLL in vhdl

How I can use PLL using language templates in RTL using VHDL. I am getting a lot of errors when importing template in my RTL. It is some changes I need to come. Its a bit confusing. Can anybody help?

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bruce_karaffa
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Registered: ‎06-21-2017

Show your code and the error messages.  Otherwise we are just guessing.

dpaul24
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Registered: ‎08-07-2014

@vishalbk ,

Screenshots?

Elaboration of the problem?

Error messages?

Well after you configure and add the PLL to your project, Vivado will generate the instantiation template for it (loop under the IP drop-down). Look for the file with extension .vhd. Copy the code from that file and use it where you want to put the PLL.

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vishalbk
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[Synth 8-2032] formal bandwidth is not declared [/home/visba128/thesis/extra/NNLS_AFTERARCH/NNLS/Synthesizable code/NNLS_control.vhd:274]

This is the error message.

 

component PLLE2_BASE is

port (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
SIGNAL CLKOUT0 : STD_LOGIC; -- 1-bit output: CLKOUT0
SIGNAL CLKOUT1 : STD_LOGIC; -- 1-bit output: CLKOUT1
SIGNAL CLKOUT2 : STD_LOGIC; -- 1-bit output: CLKOUT2
SIGNAL CLKOUT3 : STD_LOGIC; -- 1-bit output: CLKOUT3
SIGNAL CLKOUT4 : STD_LOGIC; -- 1-bit output: CLKOUT4
SIGNAL CLKOUT5 : STD_LOGIC; -- 1-bit output: CLKOUT5
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
SIGNAL CLKFBOUT : STD_LOGIC; -- 1-bit output: Feedback clock
SIGNAL LOCKED : STD_LOGIC; -- 1-bit output: LOCK
SIGNAL CLKIN1 : STD_LOGIC; -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
SIGNAL PWRDWN : STD_LOGIC; -- 1-bit input: Power-down
SIGNAL RST : STD_LOGIC; -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
SIGNAL CLKFBIN : STD_LOGIC -- 1-bit input: Feedback clock
);
end component;

U_9: PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 2, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)

port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
LOCKED => LOCKED, -- 1-bit output: LOCK
CLKIN1 => clock, -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => reset_in, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock
);

This is the code, I cant figure out what I am missing

 

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dpaul24
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Registered: ‎08-07-2014

@vishalbk ,

NNLS_control.vhd:274

I should also know what is at line 274. I cannot go line by line through your RTL and find the mistake!

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vishalbk
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Registered: ‎03-21-2020

U_9: PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW

 

This is the the line.

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