I am using a few FIFO Generator v4.3 asynchronous FIFOs in my design to synchronize data between clock domains. I am having intermittent problems with one particular FIFO coming out of reset. About 1 in 10 times the FIFO comes out of reset with one piece of data in it. The write side of the FIFO is operating at 266MHz and the read side is 75MHz. The write side is 40 bits and the read is 10 bits. The write and read clocks are completely unrelated. Most of my logic comes out of reset after a few DDR2 memory controllers signal that their initialization is complete. That asynchonous reset is propogated to a half dozen local syncrhonous reset chains (as described in WP272). Suppose I have 2 synchronous resets available (one synchronous to the read clock and the other synchronous to the write). Which do I wire to the core generated FIFO's "rst" pin? From reading the fifo user guide, it appears that the asynchronous reset is rising edge sensitive. If this is the case, should I reset my FIFO with a local state machine immediately after the rest of my logic flops have come out of reset?
The question: what's the preferred method of resetting an asynchronous FIFO?