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Registered: ‎09-02-2013

Problem Reading from Fifo (Fifo generator v6.2 , ISEv 12.2)

Hi ,


I have two fifo in my design  one Fifo_11x1024 ( 11 bit wide and 1024 deep)and other is Fifo_8x4096( 8 bit wide and 4096 deep) . Both have a common read write clock and that is 80 Mhz .


I read from Fifo_11x1024 and write top 8 MSB to Fifo_8x1046 . What i have observered , if i do this for N words then (N-1) word is written correctly on Fifo_8x4096 but he Nth word i.e the last word is undefined random number.


For e.g if I read 100 words from Fifo_11x1024  and write to Fifo_8x4096 , then 99 is written correctly and 100th word is undefined. If i read 5 words , 4 written correctly 5th undefined.


So problem comes , when i want to read only 1 word .It always come undefined and never written correctly in fifo_8x4096.


In behavioural simulation everything seems fine and all N words written corretly . But after Implementation designs goes bonker on last word.


Anyone any idea.



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Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

1. You can try with latest version of core.

2. We have provided example test bench with the core. See if you can reproduce the issue.

3. what is your core configuration. Check the debug section in product guide and make sure all the inputs signals drived properly.

Thanks and Regards
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