Problem with Fifo read (Kintex 7)

[pspear@dwavesys.com]

I have run into a timing problem with the Corgen 9.3 Fifo generator IP. I'm using a 34x8192 deep, FWFT, Native Interface, Block Ram common clock fifo with almost full and almost empty flags.

The following is an ILA capture of the problem. rx_d is the fifo input and rx_src_rdy is the write enable. The other signals should be self evident.

The circled assertion of the read enable shows the data changing simultaneously. All the following data transition have the same problem. It is as though the ILA captured the read enable a cycle late but actually the read enables are occuring exactly as intended in the design.

The following is a simulation of the same

It appears to me that there is a timing violation in the compile. I'm using ISE14.6.

Anyone have any suggestions, solutions or work arounds?

Thanks

Peter Spear

[pspear@dwavesys.com · Accepted solution]

Oops. I spotted the problem. The fifo data was coming from one of two aurora links on the board. I failed to correctly deal with the different clock on the second link. The fifo needed to be a dual clock design.