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havok
Visitor
Visitor
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Registered: ‎01-10-2020

Problems with BRAM read/write processes

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Hello all,

I have written a simple test code to test the BRAM's read and write processes. I use true dual port BRAM. I try to write data to first two addresses by using port A and try to read these data from port B. However, I cannot see any data changes on port B output. 

Here is my code:

always @ (posedge CLK) begin
    if(!ARESETN) begin
        bram_test_state <= 4'd0;
        bram_test_addr_r <= 32'd0;
        bram_test_wea_r  <= 4'd0;
        bram_test_din_r  <= 32'd0;
        bram_test_en_r   <= 1'b0;
        bram_cd_en_r     <= 1'b0;
        bram_cd_addr_r   <= 32'd0;
    end
    else begin
        case(bram_test_state)
            4'd0: begin
                if(Select_CV == 2'b01) begin
                    bram_test_en_r <= 1'b1;
                    bram_test_state <= 4'd1;
                end
            end
            4'd1: begin
                bram_test_wea_r <= 4'b1111;
                bram_test_din_r <= 32'h01234567;
                bram_test_addr_r  <= 32'd0;
                bram_test_state <= 4'd2;
            end
            4'd2: begin
               bram_test_addr_r <= bram_test_addr_r + 1'b1;
               bram_test_din_r <= 32'hFFFFAAAA; 
               bram_test_state <= 4'd3;
            end
            4'd3: begin
                bram_test_wea_r <= 4'b0000;
                bram_test_en_r  <= 1'b0;
                bram_test_state <= 4'd4;
            end
            4'd4: begin
                bram_cd_en_r <= 1'b1;
                bram_cd_addr_r <= 32'd0;
                bram_test_state <= 4'd5;
            end
            4'd5: begin
                bram_cd_addr_r <= 32'd1;
                bram_test_state <= 4'd6;
            end
            4'd6: begin
                bram_cd_en_r <= 1'b0;
            end 
        endcase
    end
end

Testbench:

bram.PNG

 

Thank you in advance.

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1 Solution

Accepted Solutions
markgraf
Adventurer
Adventurer
924 Views
Registered: ‎04-04-2018
Looks like your reset to BRAM is high. It needs to be driven low to release.



Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

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7 Replies
markgraf
Adventurer
Adventurer
976 Views
Registered: ‎04-04-2018
What version of Vivado?
What device?
How is BRAM configured?
Can you post a picture of the instantiation?

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
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havok
Visitor
Visitor
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Registered: ‎01-10-2020

Hello Steve,

The version is 2017.4.

The device is Zynq 7020.

It is cinfigured as true dual port.

And sorry, I cannot post the instantiation because it is company property. 

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drjohnsmith
Teacher
Teacher
952 Views
Registered: ‎07-09-2009
Are you instantiating or inferring your BRAM ?
( inference is best IMHO )

There are many options on instantiating a BRAM,
such as which has priority read or write when address on read and write port are the same,

Just as a point of interest, why do you bother resting the state machine, at start up of the fpga, all registers are pre defined, an no matter what whats the machine powers up in it will get back to state zero.

BTW :

Being primarily a VHDL designer of more fail safe designs, I have it ingrained to have a default case in all case statements, and have all output states of the case defined in all steps.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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havok
Visitor
Visitor
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Registered: ‎01-10-2020

Hello John,

I use instantiation for BRAM controls. I have added inputs and outputs to my IP for controlling BRAM. I have not created a specific module for BRAM control. I have written a sub state machine in my main state machine module to control BRAM. And about that resetting, yes I know but I tried to be safe.

Have you noticed something odd about my code or the testbench image? Because I cannot find any problematic part.

Thank you in advance.

 

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drjohnsmith
Teacher
Teacher
938 Views
Registered: ‎07-09-2009
You say reset is safe , ah well we wont go any further on that.

Your code, we have not seen your code, only part of a state machine, so its impossible to say more.

My guess is its how you have instantiated the BRAM,

If you wont show your code, how about showing the simulation at the BRAM level not some top level signals ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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havok
Visitor
Visitor
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Registered: ‎01-10-2020

BRAM signals of Port A:

bram2.PNG

I have modified the code to read just from Port A. I have commented the parts where I control the Port B signals and set the "en" of Port A always high for read process. 

 

Thank you in advance.

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markgraf
Adventurer
Adventurer
925 Views
Registered: ‎04-04-2018
Looks like your reset to BRAM is high. It needs to be driven low to release.



Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

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