Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎01-23-2019

Push data from PL to BRAM


I got a problem with pushing data from my IP Core to Block RAM. My block design is here:








In one turn, when I send command to my IP Core (push_data) (via AXI-Lite), it needs to push 5000 instances to BRAM. Then I will use CDMA to transfer data from BRAM to my DDR.

The transfer from BRAM to DDR is no problem. But the transfer from my IP Core to BRAM doesn't seem to work.

Each time my IP Core push data it will (sequentially):

  • Set the ena_a to HIGH
  • Set rst_a to HIGH then LOW to reset
  • Simultaneously set we_a[3:0] to 0xF in 5000 clock cycles, increment addr[31:0] from 0 to 4999 and make data to transfer ready at din_a[31:0].

After I transfer data from BRAM to DDR, I print the data transfered and it is 0xFFFFFFFF and 0x00000000. It seems like this is default data of BRAM, not my data from my IP Core.

Please help me with this problem. Is there anything wrong in my implementation?

Thank you


0 Kudos
0 Replies