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11,276 Views
Registered: ‎09-24-2008

QDR2 interface problem with MIG2.0

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Dear all ,

       currently i am working on QDR2 and DDR2 interface with Vertex5, for this i used MIG2.0 to generate RTL code,

       i used the code to simulate, in this "call_done" is not goes high at all

       if any one worked on this please help me very urgent

 

Fhz : 200MHZ

 

Regards

Venkatesan.K

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zhex
Xilinx Employee
Xilinx Employee
16,560 Views
Registered: ‎08-07-2007
In MiG2.0, an example testbench is provided. You could run sim.do in mig_20\example_design\sim\ in Modelsim and this will give you a good start and you could then refer to the test bench.

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zhex
Xilinx Employee
Xilinx Employee
16,561 Views
Registered: ‎08-07-2007
In MiG2.0, an example testbench is provided. You could run sim.do in mig_20\example_design\sim\ in Modelsim and this will give you a good start and you could then refer to the test bench.

View solution in original post

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