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Registered: ‎09-09-2019

Quad SPI transaction width of 64-bit is needed. The core is limited to 32-bit transaction width.

My FPGA device is Zynq7014. I have used the Quad SPI IP to interface with 4x16-bit register driver chips. These chips are daisy chained on the board, the Spi_CLK and Spi_CS is connected to all 4 chips, where the MOSI is connected to the first chip and we need to clock in 64 bit of data in to have all 4 registers filled in each transaction.

The core transaction width is 32-bit maximum, and we need 64-bit for each transaction. My question is how can we control the CS to stay low for 2x32-bit transactions? Is it possible to do this from the processor side? or we can only do it from the FPGA? Has anyone done this so far who could help us? 



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