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526 Views
Registered: ‎02-02-2020

Question about SYNC of JESDIP and PLL lock signal of IP

XCKU15P-2FFVA1156E and Texas Instruments ADC in JESD204B subclass 1
It is used by connecting 16 lanes of 8 lanes x 2 lanes.
This is one-way communication from ADC to FPGA.

However, the SYNC signal sometimes drops during data transmission from the ADC
I am having trouble rerequesting the JESD link.

Could you tell me under what conditions this link rerequest occurs?
There may be various factors, but I would appreciate it if you could tell me a wide range of possibilities.

I have one more question.
I would like to monitor the PLL in JESDIP and the PLL lock signal in the memory controller IP.
Could you tell me how to take this out?

Please tell me the above two points.

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3 Replies
raj
Adventurer
Adventurer
393 Views
Registered: ‎05-24-2020

shogo.hanawa.ud@hitachi-hightech.com 

 

Could you tell me under what conditions this link rerequest occurs?

https://www.xilinx.com/support/answers/66921.html

I would like to monitor the PLL in JESDIP and the PLL lock signal in the memory controller IP.
Could you tell me how to take this out?

Add gt_cplllock/gt_qll0lock/gt_qpll1lock signal to chipscope to monitor it.

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rkhatri
Moderator
Moderator
354 Views
Registered: ‎01-10-2019

Hi shogo.hanawa.ud@hitachi-hightech.com ,

Once in SYNC, there are 3 main reasons a system may fall out of sync / request a resync:
1) CGS is lost on any lane
2) Incorrect transition from 0xBC to the start of ILA is detected
3) Misalignment in received data is detected (alignment codes in data detected at unexpected positions)
- A resync will be triggered when 8 succesive multiframe alignment characters are detected in unexpected places (not at end of multiframe)

If sync is lost shortly after being achieved, could indicate the ADC / DAC settings do not match the JESD204 core settings
1) Settings of ADCs / DACs must match those of the JESD204B core
2) F (octets per frame)
3) K (frame per multiframe)
4) Scrambling / descrambling setting
5) Subclass mode
6) SYSREF handling

 

Thanks,
Rahul Khatri
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350 Views
Registered: ‎02-02-2020

My circuit had two RXs of JESD204B and used them to receive two 8-lane signals.

It turns out the trouble stems from a lack of synchronization between the two RXs. The problem was solved by reconfiguring the circuit to synchronize.


Thank you.

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