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davidhuo
Observer
Observer
9,682 Views
Registered: ‎11-02-2012

Questions about BRAM INIT value

I create a ROM rom_4096X12 , initial it wih value like this in coe:

 

33  22  11  00

77  66  55  44

BB AA  99  88

FF EE DD CC

.......repeat......

 

when it is finished implement, I opened it by fpga_editor, the mem had been mapped to 4 BRAM32

 

the value of each BRAM32 are all repeat, here is the INIT_00 of 4 BRAM32

 

ram[0]: INIT_00:  ......cc884400 (repeat 256bit)

ram[1]: INIT_00: .. .....6E4C2A08

ram[2]: INIT_00:... ....FBEAD9C8

ram[3]:INIT_00: ... ...1F170E06

 

the ram[0] is correct , it is the low 8bit value of ROM

 

but the ram[1:3] is not follow that rule

 

I suspect ram[1] shift 1 bit right, ram[2] shift 2 bits right , I can't figure out  the value of rom[4]

 

My question is how to use data2mem when the rom value has been encode ?

 

 

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gszakacs
Professor
Professor
9,662 Views
Registered: ‎08-14-2007

First I think there is a typo in your post.  You say 4096x12, but I suspect you meant to say 4096x32?

 

I think you're right about shifting.  It looks like CoreGen has used the "parity" bit of each RAM to generate a 9-bit wide 4K deep memory from each BRAM, even though it could have had enough bits using only 8-bit wide memory.  So the "missing bit" between the BRAMs must be stored in the parity bit using a separate initialization string.

 

It's likely that you'll have problems using this memory with data2mem.  There may be a way to force Coregen to use only the 8 "data" bits by telling it which primitive to use.  If not you may need to code this a different way in order to use data2mem.

 

By the way the 4th memory seems to follow the pattern (Upper bits shifted right three) so it only provides the upper 5 bits of the 32-bit wide memory.

-- Gabor
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balkris
Xilinx Employee
Xilinx Employee
9,597 Views
Registered: ‎08-01-2008

Have your tried with read back these value. this may be usability issue. I think you need perform read. Have you tried in simulation
Thanks and Regards
Balkrishan
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