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Participant
Participant
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Registered: ‎02-08-2016

RAMB18E cascade connectivity issue

I want to connect 3-RAMB18E2 modules in a cascaded fashion as shown in UG573 Page 23 Figure 1-11.

 

But I am not sure, how do I configure ports A and B.

 

for "FIRST" BRAM in cascade : I am using port DINBDIN for data input. Port A- read mode & Port B - write mode

for "MIDDLE" BRAM in cascade : I am using port CASDINB for input. Port A- read mode & Port B - write mode. My question is -

 

How do data read from Port A (FIRST BRAM) goes into CASDINB  of MIDDLE BRAM when FIRST BRAM port B is configured as WRITE??

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Moderator
Moderator
709 Views
Registered: ‎08-08-2017

Hi @gtushar

 

Standard Data out cascade and Data in cascade connectivity diagrams are given on page 20 to 23 of memory user guide

https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf

 

Additionally , What is the requirement of cascading memories here manually ? I mean is the specific reason for not using

block memory generator IP or XPM_Memory based implementation ?  Where cascading is done by tool itself.

 

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