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Registered: ‎06-30-2013

REF_CLK source for GMII to RGMMI v4.0 IP core

I am implementing the second Gigabit Ethernet MAC (GEM) in a Zynq 7Z030 that is integrated onto a PicoZed Module (AES-Z7PZ-7Z030-SOM-I-G/REVE).  The plan is to use EMIO to bring in the GMII intyerface from the second GEM and connect that interface to the GMII to RGMII IP as described in PG160.  This will give two separate gigibit Ethernet interfaces from the PicoZed and my main motherboard card that supports the PicoZed.

My plan is to use internal clocking and as I understand it I need to supply a 200MHz ref_clkK into the IP.  I believe this clock is used for clocking internal IDELAYE elements or the like.

I have an external 100MHz clock oscillator that I feed into the Zynq PL fabric.  My plan is to feed the 100MHz clock into an MMCM and multiply by 2 to obtain a 200MHZ clock to feed the ref_clk input of the IP.

The board clock has reasonable stability and phase noise but is not ultra low jitter.  I believe the REF_CLK quality does not have to be critical so taking it from the MMCM X2 output should be adequate. 

Is my understanding correct?  Is there anything I else I need to know about the internal clocking of the this IP?

Thanks for any guidance that can be provided


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