Are you guys aware of any IP from Xilinx or opensource project that uses a ROM (possible generated by BMG)
initialized by a COE file and use that content to generate AXI Master transactions? My Idea is each COE data line
be one AXI Master transaction...
I've looked at the AXI Traffic Generator, but it doesn't fit well on what I need....
It is a fairly simple RTL design, but if there's any out there, I'd like to use it right away.