11-30-2020 04:43 AM
11-30-2020 04:58 AM - edited 11-30-2020 04:59 AM
It all depends how much die real-estate do you have after design implementation.
16 x 256 bits isn't a huge size. If there are enough resources left after design Impl, go ahead with LUT implementation. BRAMs can always be used but they have their latency.
For 7 series FPGAs there is something called distributed RAM which are useful resources for small memories something like you want to implement. You can refer to this thread:
If I was using a 7 Series FPGA, for your case, I would have used a distributed RAM.
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11-30-2020 06:09 AM
12-06-2020 01:39 AM - edited 12-06-2020 01:44 AM
How could I infer the ROM in RTL code? What attribute should I use?
There is ROM_STYLE attribute, but you need explicitly define the ROM style - either BRAM or Distributed. So, how to make the tool doing this automatically according to the memory size, etc?
12-06-2020 10:29 AM
You need to look into UG901