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Observer
Observer
368 Views
Registered: ‎09-10-2020

ROM implementation -> by BRAM or LUTs?

Hi All,

What is a criteria for the ROM implementation? When to choose it should be implemented by BRAM and when by LUTs?
 
Let's say I need to implement the 4*256 ROM (4bits address, 256bits data). Should it still be implemented by BRAMs?
 
Thank you!
 
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Scholar
Scholar
361 Views
Registered: ‎08-07-2014

@ldm_gk,

It all depends how much die real-estate do you have after design implementation.

16 x 256 bits isn't a huge size. If there are enough resources left after design Impl, go ahead with LUT implementation. BRAMs can always be used but they have their latency.

For 7 series FPGAs there is something called distributed RAM which are useful resources for small memories something like you want to implement. You can refer to this thread:

https://forums.xilinx.com/t5/Welcome-Join/Block-ram-versus-Distributed-ram-on-7-series-FPGA/td-p/517513

If I was using a 7 Series FPGA, for your case, I would have used a distributed RAM.

------------FPGA enthusiast------------
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Teacher
Teacher
337 Views
Registered: ‎07-09-2009

One other way to look at this
if you code in a HDL such as VHDL or Verilog,
and you infer the ROM,
then the tools will / should select what fits best.

It can be tricky , as is mentioned, the block rams to make a decent speed need to use the registered ram output, were as SRL ram does no

But generally, ensure there is an output register,
and for ram don't use a clear, and the tools will do a good job of selecting .

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Observer
Observer
264 Views
Registered: ‎09-10-2020

How could I infer the ROM in RTL code? What attribute should I use?

There is ROM_STYLE attribute, but you need explicitly define the ROM style - either BRAM or Distributed. So, how to make the tool doing this automatically according to the memory size, etc?

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Teacher
Teacher
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Registered: ‎07-09-2009

You need to look into UG901

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf

 

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