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Explorer
Explorer
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Registered: ‎10-12-2018

RX Aurora holds back one 64b word

The issue

I have seen, that Aurora holds back one 64bit word all the time, in my configuration (see below). I guess, the problem is related to the framing mode. Aurora transmit the current word, only if the tlast has been asserted, or a next word has arrived. So inspite of "core has no built-in buffer for user data, and there is no m_axi_rx_tready signal on the RX AXI4-Stream interface" from pg11.2 the RX core holds back the last word.

My experiments:

I don't used the tlast signal in some (debug) mode of my design. I sends bursts of dummy data (counter) without tlast. I see the last counter value at the begin of the new burst, then the correct counter values. The issue solves if I insert tlast, or if I reset the receiver Aurora core.

If the previous burst was terminated with tlast: The data starts from "0" (OK)

after_tlast1.PNG

If the previous data burst was NOT terminated with tlast, the last counter value can be seen at the beginning of the new burst. (I have waited several minutes between the two bursts)

after_NO_tlast1.PNG

I use:

  • Vivado 2017.4
  • Aurora 11.2
    • RX-only Simplex
    • Framing mode
    • 2Gbps
    • Single-lane
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Teacher
Teacher
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Registered: ‎07-09-2009

have a look at gorans reply

https://forums.xilinx.com/t5/Processor-System-Design/AXI-handshaking-process-VALID-READY/td-p/454000

 

 

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Highlighted
Explorer
Explorer
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Registered: ‎10-12-2018

Note, that RX-Aurora has no tready, so handshaking is irrelevant in this case.

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