10-11-2019 08:01 AM
The example code generated when you right click on the IP , is just for simulation and demosration of how the IP works.
There should be a tech ref design ( TRD ) for the board,, hunt that down if you dont have it already, and that will work out the box on your board,
Its often ( always ) easier to modify a working board file rather than start from zero,
that way you cna make small chnages and go back when it stops working.
10-10-2019 11:29 AM
Hello, I'm a newbie here with Vivado and the 8b/10b IP Core. I'm reading on page 33 of the LogiCORE IP Aurora 8b/10b v8.3 and it talks about "example_design" and that first-time users should use this template. Where is this example design?
10-10-2019 12:31 PM
10-11-2019 12:34 AM
Yes, it is possible, but you will need to set the correct pin assignment to your design.
- If your example design is one lane :
Please use Bank225. You can use SMA cables for one-lane loopback test.
I would suggest you to start with one lane.
- If your example design is multiple lanes : you can use Bank226 or Bank227. You need additional board to connect Aurora TX to RX lanes.
Probably something like this XM107 board (https://www.xilinx.com/support/documentation/boards_and_kits/ug539.pdf) can fit your test usecase.
Thanks & regards
10-11-2019 01:08 AM
The generated file is for simulatoin and information only,
its not aimed at your board, its to demonstrate ( if you read verilog ) how to use the IP,
10-11-2019 07:24 AM
Hello, thank you for responding to my message. I am very exciting to try this out. I have a SFP+ transceiver that I would like to try this out on. Right now I'm try to read over all the verilog files and see how things fit together. Quick question for you, I see in the code they they instantiate a IBUFDS_GT4, I'm planning on doing everything in the the IP Integrator Block design so is that available from the IP Catalog?
10-11-2019 07:35 AM
Hello, I'm a little confused, if I go to the Project Manager Setttings I see:
It shows the board that I am using. Is this not correct, I won't be able to run this example on this board? I was thinking to test out the SFP+ interface using a fiber transceiver (FTLF1326P3BTL). I understand that I still need to connect the IP TX/RX differential pairs to the SPF+ pins as described on page 81 of the ZCU106 Evaluation Board. I'm a newbie with the Xilinx tools so I may not be quick to understand how things are fitting together. I like using the IP Integrator Block Design to see things.
I was hoping I could get things working, does this sound possible?
10-11-2019 03:36 PM
Hello, quick question for the forum gurus. I going through the example design and I see in the Synthsis Schematic the following block:
Are these additional IP available from the IP Catalog or are they are of the Aurora 8b/10b IP?
I looked in the IP Catalog and I don't find LL_TO_AXI or AXI_TO_LL.
I ask because I will be using the IP Integrator Block Design to place the Aurora IP and I wasn't sure what other blocks I need to add to the design.
10-11-2019 03:42 PM
Hello, another question from a newbie learning Vivado. I again looking at the Aurora 8b/10b example, I'm looking at the Synthesis Schematic:
I've only done a little work in Vivado, particularly in the Block Design Tool. I have a question about IBUFDS. I understand it converts the differential pairs to signal ended but I don't see that in the IP Catalog. It is inferred from the constraints file in which you define the diff pairs?
10-11-2019 04:01 PM
Hello, would it be possible to map the TX and RX diff pairs of the design to the diff pairs on the SFP+ and also map the appropriate clocks to the design? Seems like I only need to do some pin assignments and I should have things ready to try the design on the board.