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Teacher drjohnsmith
Teacher
440 Views
Registered: ‎07-09-2009

Re: Aurora 8b/10b Example

The example code generated when you right click on the IP , is just for simulation and demosration of how the IP works.

There should be a tech ref design ( TRD ) for the board,, hunt that down if you dont have it already, and that will work out the box on your board,

   Its often ( always ) easier to modify a working board file rather than start from zero,

     that way you cna make small chnages and go back when it stops working.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
11 Replies
Voyager
Voyager
563 Views
Registered: ‎12-07-2018

Aurora 8b/10b Example

Hello, I'm a newbie here with Vivado and the 8b/10b IP Core. I'm reading on page 33 of the LogiCORE IP Aurora 8b/10b v8.3 and it talks about "example_design" and that first-time users should use this template. Where is this example design?  

 

Thanks,

Joe

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Teacher drjohnsmith
Teacher
550 Views
Registered: ‎07-09-2009

Re: Aurora 8b/10b Example

In vivado, once you have created and generated the IP,
right click on the ip generated ( XCI file ? )
and you get option to generate example design,

accept and a new instance of vivado will open with the example design, and the path shown at the top of the GUI.

BTW: hope you speak Verilog, as Xilinx dropped support for VHDL, so unless you do speak Verilog ,the example is useless,



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Voyager
Voyager
533 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Hello, I got the example generated as your said thank you. Can I run that on the ZCU106 board?

Joe

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Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎03-30-2016

Re: Aurora 8b/10b Example

Hello @joe306 
  

ZCU106_Aurora_Loopback.png  

Yes, it is possible, but you will need to set the correct pin assignment to your design.

- If your example design is one lane :
  Please use Bank225. You can use SMA cables for one-lane loopback test.
  I would suggest you to start with one lane.

- If your example design is multiple lanes : you can use Bank226 or Bank227. You need additional board to connect Aurora TX to RX lanes.
  Probably something like this XM107 board (https://www.xilinx.com/support/documentation/boards_and_kits/ug539.pdf) can fit your test usecase.

XM107.png

Thanks & regards
Leo

Teacher drjohnsmith
Teacher
489 Views
Registered: ‎07-09-2009

Re: Aurora 8b/10b Example

The generated file is for simulatoin and information only,

its not aimed at your board, its to demonstrate ( if you read verilog ) how to use the IP,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Voyager
Voyager
445 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Leo,

 

Hello, thank you for responding to my message. I am very exciting to try this out. I have a SFP+ transceiver that I would like to try this out on. Right now I'm try to read over all the verilog files and see how things fit together. Quick question for you, I see in the code they they instantiate a IBUFDS_GT4, I'm planning on doing everything in the the IP Integrator Block design so is that available from the IP Catalog?

 

Thanks,

Joe

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Voyager
Voyager
442 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Hello, I'm a little confused, if I go to the Project Manager Setttings I see:

board.jpg

 

It shows the board that I am using. Is this not correct, I won't be able to run this example on this board? I was thinking to test out the SFP+ interface using a fiber transceiver (FTLF1326P3BTL). I understand that I still need to connect the IP TX/RX differential pairs to the SPF+ pins as described on page 81 of the ZCU106 Evaluation Board. I'm a newbie with the Xilinx tools so I may not be quick to understand how things are fitting together. I like using the IP Integrator Block Design to see things. 

I was hoping I could get things working, does this sound possible? 

Very Respectfully,

Joe

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Voyager
Voyager
410 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Great! I'm off to looking for "tech ref design" ( TRD ) for the board?

Thank you,
Joe

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Voyager
Voyager
382 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Hello, quick question for the forum gurus. I going through the example design and I see in the Synthsis Schematic the following block:

 

traffic.frame_gen_ll_to_axi_pdu_i

traffic.frame_gen_i

traffic.frame_chk_axi_to_ll_pdu_i

 

Are these additional IP available from the IP Catalog or are they are of the Aurora 8b/10b IP?

I looked in the IP Catalog and I don't find LL_TO_AXI or AXI_TO_LL.

I ask because I will be using the IP Integrator Block Design to place the Aurora IP and I wasn't sure what other blocks I need to add to the design.

Thank you,

Joe

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Voyager
Voyager
372 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Hello, another question from a newbie learning Vivado. I again looking at the Aurora 8b/10b example, I'm looking at the Synthesis Schematic:

IBUFDS.jpg

I've only done a little work in Vivado, particularly in the Block Design Tool. I have a question about IBUFDS. I understand it converts the differential pairs to signal ended but I don't see that in the IP Catalog. It is inferred from the constraints file in which you define the diff pairs?

 

Thanks,

Joe

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Voyager
Voyager
353 Views
Registered: ‎12-07-2018

Re: Aurora 8b/10b Example

Hello, would it be possible to map the TX and RX diff pairs of the design to the diff pairs on the SFP+ and also map the appropriate clocks to the design? Seems like I only need to do some pin assignments and I should have things ready to try the design on the board.

Comments?

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