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petersanch
Observer
Observer
2,538 Views
Registered: ‎04-14-2017

Read BRAM Contents From Vivado Block Design

I'm new to Vivado and the Block Design.

Here is my block design after one of the Xilinx videos. It synthesizes but how do I read contents of the BRAM? I want to have 1 port connected to the DMA block and 1 connected to custom HDL module so I can read the contents without using AXI interface. Is that possible? How can I do that?

 

vivado-block.jpg

 

Cheers

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kelemixx
Contributor
Contributor
2,522 Views
Registered: ‎11-21-2014

Hi,

You can config the "AXI BRAM Controller" using only on port (PORTA) and connect it to "Block Memory Generator". Then you can mark PORTB of BRAM as external and connect to your HDL.

Thus both DMA and your HDL can access the BRAM at the same time.
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petersanch
Observer
Observer
2,485 Views
Registered: ‎04-14-2017

Thanks. I will try that now. For whatever reason the AXI BRAM Controller is limiting the Block Memory Generator memory depth to 1024. It wont let me change the number in the box. Does any one know how do I change that?

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kelemixx
Contributor
Contributor
2,479 Views
Registered: ‎11-21-2014

Double click "Block Memory Generator" and see the "mode". You must using "BRAM Controller". For this mode, Depth is auto inferred from your AXI Address config.

Change the "mode" to "stand alone" may help you.
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