11-21-2017 04:49 PM
I'm new to Vivado and the Block Design.
Here is my block design after one of the Xilinx videos. It synthesizes but how do I read contents of the BRAM? I want to have 1 port connected to the DMA block and 1 connected to custom HDL module so I can read the contents without using AXI interface. Is that possible? How can I do that?
11-21-2017 05:33 PM
11-21-2017 07:29 PM
Thanks. I will try that now. For whatever reason the AXI BRAM Controller is limiting the Block Memory Generator memory depth to 1024. It wont let me change the number in the box. Does any one know how do I change that?
11-21-2017 09:26 PM