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Spandana
Visitor
Visitor
433 Views
Registered: ‎11-29-2020

Reading and Writing from BRAM does not seem to work

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Hi,

I am trying to :
1. write an array into BRAM addresses in Vitis
2. Read these values in VHDL from Vivado
3.Write the values which are read from VHDL back into same BRAM but at another address range . This way I can make sure that data is being copied properly.

But at 3rd step, when I print out the values, everything is zero.

I tried to set some value by hand at one address in vhdl and then read from Vitis but that does not seem to work either.I made sure the address ranges do not exceed and data size are compatible.

I have attached screenshots from Vivado and Vitis.Any comment/suggestion would be very helpful.

Screenshot (225).png
Screenshot (227).png
Screenshot (226).png
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drjohnsmith
Teacher
Teacher
365 Views
Registered: ‎07-09-2009

by using both edges you are halfing the available time for setup, i.e. halfing the possible speed.

Use only the positive edge,

   and set up the clock constraints as a minimum, 

   and the tools will ensure that the design meets set up / hold time,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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4 Replies
drjohnsmith
Teacher
Teacher
417 Views
Registered: ‎07-09-2009

and the simulation says what ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
bruce_karaffa
Scholar
Scholar
395 Views
Registered: ‎06-21-2017

I agree with @drjohnsmith , you need to simulate your VHDL.  I would suggest using all signals instead of variables.  Variables may behave differently than you expect.  Also, why are you clocking on the falling edge of the clock?

Spandana
Visitor
Visitor
384 Views
Registered: ‎11-29-2020

Hi,I have to look into how to simulate a block diagram in Vivado. And falling edge because in BRAM read or write happens rising edge. I want to make sure to set an address before the rising edge comes.

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drjohnsmith
Teacher
Teacher
366 Views
Registered: ‎07-09-2009

by using both edges you are halfing the available time for setup, i.e. halfing the possible speed.

Use only the positive edge,

   and set up the clock constraints as a minimum, 

   and the tools will ensure that the design meets set up / hold time,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post