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benjaminfell
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Registered: ‎09-11-2012

SEM Core External Shim with SPI Configuration Flash

Hello Fellow Engineers,

 

    On Kintex-7, can the configuration Flash SPI bus be shared with the external shim SPI pins for the Xilinx Soft Error Mitigation(SEM) core? I would like to only have one configuration flash for the both initial configuration of the FPGA and for the SPI flash used by the SEM core. This is asking if I can have multiple masters on the SPI bus used for configuration. One master would be the configuration specific pins of the FPGA with the hardcore SPI master on the FPGA. The other master would be a separate interface in the FPGA fabric that would be used by the SEM core for the replace methodology of soft error resolution. I appreciate any help you can provide.

 

Thanks,

              Ben

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