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698 Views
Registered: ‎03-12-2015

SPI Protocol Timing

Hi,

As we know, General SPI proocol  is 4-wire (SS(Active low), SCK, MOSI & MISO) protocol.

What is the minimum delay between SS and SCK in Mode CPHA =0  AND CPOL = 0?

What SPI specfications are followed by Xilinx ?

Thanks, 

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Teacher
Teacher
680 Views
Registered: ‎07-09-2009

"SPI" is at best a "loose" set of definitions

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

The aim is the slave receives data with plenty of set up and hold.

But SPI specifies no timing,

I dont knwo of any specification as to how long SS changes before data / clock starts


The aim of CPHA and POL,
is to cover all the four states , such that clock / data / CS are aligned such that the receiver can receive data .

Conceptually, its so the clock and CS and data either all change at the clock rising edge, or at the falling edge.

Most SPI peripherals sample their data on the rising edge of the clock, but some, on the falling edge, so to align the data and clock at the receiver you can use POL.

Most SPI slaves require data set up / hold time, so relevant clock is in the centre of the data, but some specify clock changes with data , which is what the CPHA is for.

Its also designed to take care of the typically badly routed SPI tracks on a board. where data and clock lengths are not matched.

As far as the xilinx IP is concerned, a 9000 CPLD will be a lot slower than a Ultrascale + part, and as SPI has no timing specifications, the IP is agnostic.

The data sheet you can generate for your design , based upon your timing constraints will tell you what your actual design is achieving.


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Registered: ‎03-12-2015

Thank you.

What are the acceptable range of SPI baudrate?

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Registered: ‎07-23-2019

 

Some quad SPI config flash run at 100 MHz. Of course, this applies to any other SPI chips. Quad or not. But be careful of the limitations of choosing a high speed, both in PCB layout (noise, length matching) and firmware/ software (buffers, delays, etc). SPI is considered a "low speed" protocol. In most cases, 1 or 10 MHz should be enough. If you are, let's say, reading data from a GPS module, there is no need for many MHz.

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Teacher
Teacher
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Registered: ‎07-09-2009

SPI has no specification on baud rate
its totally up to the designer of the chips and the system,

If your using certain chips, then just look up the speed they work at,

Normally, Id try to keep the SPI speed down, limited by how much data you want to move with what latency in your system,

SPI is normally single ended, and not terminated, so keeping edge pseeds down and lower baud rate, limits potential problems caused by high speed,

I have worked with "SPI" sent over differential link running at a few hundred MHz, but its normally down in the 1 to 10 MHz range and single ended.

As said before, SPI is a loose set of specifications.
If your using certain chips the options are constrained by the chips

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Registered: ‎03-12-2015

Thanks.

 

There are different types of SPI protocol.

Four wire, three wire and Quad  or dual.

Four wire protocol follows Motorola spec.

 

Is it correct?

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Teacher
Teacher
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Registered: ‎07-09-2009

Types of SPI is a bit off topic for the Xilinx Forum, 

 

try wiki

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

 

 

 

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