11-27-2019 11:35 PM
As we know, General SPI proocol is 4-wire (SS(Active low), SCK, MOSI & MISO) protocol.
What is the minimum delay between SS and SCK in Mode CPHA =0 AND CPOL = 0?
What SPI specfications are followed by Xilinx ?
11-28-2019 12:55 AM - edited 11-28-2019 12:57 AM
"SPI" is at best a "loose" set of definitions
The aim is the slave receives data with plenty of set up and hold.
But SPI specifies no timing,
I dont knwo of any specification as to how long SS changes before data / clock starts
The aim of CPHA and POL,
is to cover all the four states , such that clock / data / CS are aligned such that the receiver can receive data .
Conceptually, its so the clock and CS and data either all change at the clock rising edge, or at the falling edge.
Most SPI peripherals sample their data on the rising edge of the clock, but some, on the falling edge, so to align the data and clock at the receiver you can use POL.
Most SPI slaves require data set up / hold time, so relevant clock is in the centre of the data, but some specify clock changes with data , which is what the CPHA is for.
Its also designed to take care of the typically badly routed SPI tracks on a board. where data and clock lengths are not matched.
As far as the xilinx IP is concerned, a 9000 CPLD will be a lot slower than a Ultrascale + part, and as SPI has no timing specifications, the IP is agnostic.
The data sheet you can generate for your design , based upon your timing constraints will tell you what your actual design is achieving.
11-28-2019 03:23 AM - edited 11-28-2019 03:25 AM
Some quad SPI config flash run at 100 MHz. Of course, this applies to any other SPI chips. Quad or not. But be careful of the limitations of choosing a high speed, both in PCB layout (noise, length matching) and firmware/ software (buffers, delays, etc). SPI is considered a "low speed" protocol. In most cases, 1 or 10 MHz should be enough. If you are, let's say, reading data from a GPS module, there is no need for many MHz.
11-28-2019 05:26 AM
12-01-2019 11:44 PM
Types of SPI is a bit off topic for the Xilinx Forum,