06-09-2008 05:23 AM - edited 06-09-2008 10:08 AM
I'm trying to simulate the ML555 reference design in ModelSim v6.3f and am having problems. In ISE 9, it was working correctly and then I upgraded to ISE 10.1 IP Update 1 and now the link never (well, it hasn't after 800us) comes up (trn_lnk_up_n never goes to 0).
I think it may be to do with the secure IP because when I compile the design, I notice there are warnings:
** Warning: (vsim-3473) Component instance "pcie_internal_1_1_swift_bw_1 : pcie_internal_1_1_swift" is not bound.
Time: 0 ps Iteration: 0 Region: /board/ep_inst/ep_but2_u0_pcie_ep0_pcie_blk_pcie_ep File: C:/Xilinx/10.1/ISE/vhdl/src/unisims/unisim_SECUREIP.vhd
There are two similar warnings for gtp_dual_swift_bw_1 : gtp_dual_swift.
I notice these components are meant to be in the SECUREIP library, but there is nothing listed in this library in ModelSim. From what I've read, I thought that the secure IP library was a verilog library, but compxlib has created a mapping to C:\Xilinx\10.1\ISE\vhdl\mti_se\secureip. Is this correct?
Any help would be appreciated as I've wasted a lot of time trying to get this to work.