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praveengoyal
Contributor
Contributor
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Registered: ‎07-12-2012

Seeing Issue in FIFO for Virtex -7 using the ones generated for Virtex-5

HI 

 

I am using the FIFO generator for generating some FIFO using BLOCK RAM for Virtex-5, with different read and write clock. 

The below are the listed parameters i am using.  In Virtex 5 and 6 they worked perfectly but not in Virtex-7 device i am seeing 3 - 4 bits corrputed when the data is read back in every 128 bit read. I am using Vivado 14.2 and Virtex -7 2000T CES device. Do i need to apply any special patch as mentioned in "http://www.xilinx.com/support/answers/51580.htm"

 

CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=cg_apbfifo
CSET data_count=false
CSET data_count_width=8
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=127
CSET full_threshold_negate_value=126
CSET input_data_width=104
CSET input_depth=128
CSET output_data_width=104
CSET output_depth=128
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=8
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=8

 

Thanks

Praveen 

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1 Reply
austin
Scholar
Scholar
9,468 Views
Registered: ‎02-27-2008

Have you checked your timing report?

 

I would do that first, to make sure you have sufficient slack on all paths.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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