04-25-2020 03:00 AM
I am migrating a design from Artix-7 (xc7a200t) to Kintex-7 Ultrascale+ (xcku3p) and I need to convert my LVDS deserializer.
To generate it under Artix-7 (SelectIO Wizard) it was simple :
Now I am trying to generate equivalent design under Kintex-7 Ultrascale+ (High Speed SelectIO Wizard) and it seems more complicated :
What about [Enable N-side RX bitslice] on [Advanced] tab ? I checked Xilinx documentation, no more information given, it just repeats the name of the option as explanation.
Naively I thought output data are built both from P and N LVDS inputs (as for Artix-7). Does it mean - for Kintex-7 Ultrascale+ - that P and N signals are deserialized independently ? Can I simply uncheck [Enable N-side RX bitslice] to keep only P data to get something similar to my design in Artix-7 ? Or should I implement externally something more complicated to check correct alignment of P and N deserialized data ?
Thanks in advance for your answer.
04-26-2020 08:51 PM
Can I simply uncheck [Enable N-side RX bitslice] to keep only P data to get something similar to my design in Artix-7
-> Yes , in this case your datapath will be
LVDS P/N pair -> IBUFDS for differential to single ended -> Single ended data connected to P-side RX bitslice.
06-03-2020 02:05 AM
Thanks for your answer. And sorry for the delay of my feedback, I had switched on another project.
I am going to try this and will come back to close the discussion if it works.