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Registered: ‎03-01-2019

Sharing jesd204b between two GTP Quad in Artix-7 device

I am implementing a 4-channel JESD204B interface in XC7A75TFGG676 device, 2 channels are located on bank 213 and the other 2 located on bank 216. As there is only one reference clock available in PCB, I need to drive the both two JESD204B PHY with single reference clock input. According to Figure 2-2 of ug482_7series_GTP_Transceiver (listed below), reference clock mux exists between adjacent GTPE2_COMMON instances, how can I use these resources in block design?

 

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