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msjatxilinx
Adventurer
Adventurer
26,866 Views
Registered: ‎03-27-2013

Simulating Content Addressable Memory (CAM)

I used xapp1151 CAM design and customized it using presented perl scripts. It synthesizes without errors in ISE, but when it comes to simulation a problem arises. Simulating this core in either ModelSim 10.0C or Isim 14.2 fails due to the following errors. It seems that two arrays have different lengths, hence simulation fails. Please tell me how to resolve this issue. Thanks in advance.
ModelSim Error:
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 36 (35 downto 0). Right is 72 (71 downto 0).
# Time: 0 ps Iteration: 0 Instance: /test_ram_cam/u_cam_wrapper/top_cam/rtl_cam/mem/gblk/blkmem/gextw(0)/gcp/extd/gextd(0)/gincp/extdp/s6prim/BRAM_TDP_MACRO_inst/ramb_st/ramb18_dp_st/ram18_st File: C:/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd Line: 599
# FATAL ERROR while loading design

Isim Error:
HDLCompiler:410 - "N:/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd" Line 599: Expression has 72 elements ; expected 36
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test_ram_cam in library work failed

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msjatxilinx
Adventurer
Adventurer
26,863 Views
Registered: ‎03-27-2013

I should add that changing the two vector lengths is not an easy task, since there are too many parameters to be configured. Just to remind you, this CAM is not my own design. I just have customized it using available scripts.
Thanks
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anderson1008
Visitor
Visitor
26,771 Views
Registered: ‎10-18-2012

Hi,

 

I will assume that you use SRL16E primitive for your implementation.

 

There might be several possibilities causing the problem.

 

But please check this one first. If your CAM is configured to read-only, which means that the content has been installed into TCAM during initialization, all the length of the write ports and write match address also have to be specified in the script, although they will not be used. For example, if you have 512 16-bit entries in your TCAM, C_WR_ADDR_WIDTH should be 9 and C_DIN_WIDTH should be 512. So does the rest used ports, which also need to be specified.

 

Be sure to read the supporting file (XAPP1151) carefully before dive into your work.

 

Good luck.

 

Anderson

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balkris
Xilinx Employee
Xilinx Employee
26,227 Views
Registered: ‎08-01-2008

Make sure you have followed the xapp documentation and provided read me file .
Thanks and Regards
Balkrishan
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