05-01-2013 12:52 AM
I used xapp1151 CAM design and customized it using presented perl scripts. It synthesizes without errors in ISE, but when it comes to simulation a problem arises. Simulating this core in either ModelSim 10.0C or Isim 14.2 fails due to the following errors. It seems that two arrays have different lengths, hence simulation fails. Please tell me how to resolve this issue. Thanks in advance.
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 36 (35 downto 0). Right is 72 (71 downto 0).
# Time: 0 ps Iteration: 0 Instance: /test_ram_cam/u_cam_wrapper/top_cam/rtl_cam/mem/gblk/blkmem/gextw(0)/gcp/extd/gextd(0)/gincp/extdp/s6prim/BRAM_TDP_MACRO_inst/ramb_st/ramb18_dp_st/ram18_st File: C:/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB16BWER.vhd Line: 599
# FATAL ERROR while loading design
HDLCompiler:410 - "N:/P.28xd/rtf/vhdl/src/unisims/primitive/RAMB16BWER.vhd" Line 599: Expression has 72 elements ; expected 36
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit test_ram_cam in library work failed
05-01-2013 01:48 AM
05-24-2013 07:17 AM
I will assume that you use SRL16E primitive for your implementation.
There might be several possibilities causing the problem.
But please check this one first. If your CAM is configured to read-only, which means that the content has been installed into TCAM during initialization, all the length of the write ports and write match address also have to be specified in the script, although they will not be used. For example, if you have 512 16-bit entries in your TCAM, C_WR_ADDR_WIDTH should be 9 and C_DIN_WIDTH should be 512. So does the rest used ports, which also need to be specified.
Be sure to read the supporting file (XAPP1151) carefully before dive into your work.
10-30-2013 02:31 AM