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Anonymous
Not applicable
10,419 Views

Simulating IP cores (fifo)

Hello all,

Whether it is possible to simulate IP cores in Xilinx ise simulator.
I wrote a test bench and run the simulation.The waves for data writng is there.But when I tried to read data by pulling up rd_en, nothing has appeared  on the  dout.What will be the problem.

Thanks in advance

Abhilash.R.S

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2 Replies
Anonymous
Not applicable
10,401 Views

Hello,

Here I am stating the procedure that I followed to stimulate IP core fifo.Plese tell me whether  I am wrong in any step.

 

a)First I wrote the top module tx_fifo where I instantiate the fifo_generator_v4_3

module tx_fifo (...);

.

.

.

fifo_generator_v4_3

.

b)Then I invoke core generator and generate fifo with my requirements.I got fifo_generator_v4_3.v in core generator's project directory.

 

c)Then I add fifo_generator_v4_3.v to tx_fifo.prj by clicking add source tab.

d)I wrote the test bech and simulate it

 

The problem that I faced is ,I didn't get wr_ack eventhough I give wr_en=1 along with din=data

 

My testbench is attached here.

what is the problem

 

 

Abhilash

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ywu
Xilinx Employee
Xilinx Employee
10,381 Views
Registered: ‎11-28-2007

Can you attached the waveform? Things to try:

 

Add timesale to your testbench

Make the clock period 10 ns

 

Cheers,
Jim
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