08-10-2010 06:58 AM
Whether it is possible to simulate IP cores in Xilinx ise simulator.
I wrote a test bench and run the simulation.The waves for data writng is there.But when I tried to read data by pulling up rd_en, nothing has appeared on the dout.What will be the problem.
Thanks in advance
08-11-2010 05:11 AM
Here I am stating the procedure that I followed to stimulate IP core fifo.Plese tell me whether I am wrong in any step.
a)First I wrote the top module tx_fifo where I instantiate the fifo_generator_v4_3
module tx_fifo (...);
b)Then I invoke core generator and generate fifo with my requirements.I got fifo_generator_v4_3.v in core generator's project directory.
c)Then I add fifo_generator_v4_3.v to tx_fifo.prj by clicking add source tab.
d)I wrote the test bech and simulate it
The problem that I faced is ,I didn't get wr_ack eventhough I give wr_en=1 along with din=data
My testbench is attached here.
what is the problem