Currently i'm working with AXI_GP port. Basically I need is to read and write my IP data through AXI signals.
I have made a custom IP and stored a sine wave signal data, and in the simulation part need to read & write data from AXI_GP port master and slave signal (you can see my simulation result in attached image) but somehow i have faced some problem in simulation part, master & slave data are not in the original form of the wave that i actually want. Code that I used to change the orientation of data.(in verilog)
I can't understand what is the problem ..
PS: Yes, my custom IP ZYNQ Block diagram is synthesizable and it generate bit stream without any error.
please refer my following simulation image..
Any Suggestions and guidance would be appreciated.