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mtang
Visitor
Visitor
320 Views
Registered: ‎09-21-2019

Simulation can't be finished when using zynq vip

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Hi,

I used the example testbench for zynq block design as below:

----------------------------------------

tb_ARESETn = 1'b0;
repeat(20) @(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
$display ("%t, System reset completed", $time);

repeat(5) @(posedge tb_ACLK);

// Reset the PL
zynq_sys.zynq_bd_i.processing_system7_0.inst.fpga_soft_reset(32'h1);
zynq_sys.zynq_bd_i.processing_system7_0.inst.fpga_soft_reset(32'h0);

// This drives the LEDs on the GPIO output
zynq_sys.zynq_bd_i.processing_system7_0.inst.write_data(32'h41200000, 4, 32'hFFFFFFFF, resp);

$display ("%t, running the testbench, data read from GPIO was 32'h%x", $time, read_data);

//Write into the BRAM through GP0 and read back
zynq_sys.zynq_bd_i.processing_system7_0.inst.write_data(32'h40000000, 4, 32'hDEADBEEF, resp);
zynq_sys.zynq_bd_i.processing_system7_0.inst.read_data(32'h40000000, 4, read_data, resp);
$display ("%t, running the testbench, data read from BRAM was 32'h%x", $time, read_data);

-----------------------------------------------------------

and the simulation output below:

-------------------------------------------------

## current_wave_config
Block Memory Generator module tb.zynq_sys.zynq_bd_i.blk_mem_gen_0.inst.native_mem_mapped_module.blk_mem_gen_v8_4_4_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.M_AXI_GP0.master
[0] : *ZYNQ_VIP_INFO : M_AXI_GP0 : Port is ENABLED.
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.M_AXI_GP1.master
[0] : *ZYNQ_VIP_INFO : M_AXI_GP1 : Port is DISABLED.
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_GP0.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_GP0 : Port is DISABLED.
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_GP1.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_GP1 : Port is DISABLED.
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_HP0.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_HP0 : Port is DISABLED.
0 BEFORE checking line ...... x
0 AFTER checking line ...... x
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_HP1.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_HP1 : Port is DISABLED.
0 BEFORE checking line ...... x
0 AFTER checking line ...... x
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_HP2.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_HP2 : Port is DISABLED.
0 BEFORE checking line ...... x
0 AFTER checking line ...... x
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_HP3.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_HP3 : Port is DISABLED.
0 BEFORE checking line ...... x
0 AFTER checking line ...... x
XilinxAXIVIP: Found at Path: tb.zynq_sys.zynq_bd_i.processing_system7_0.inst.S_AXI_ACP.slave
[0] : *ZYNQ_VIP_INFO : S_AXI_ACP : Port is DISABLED.
0 ns, Running the tb
0 else checking line ......0
410 ns, System reset completed
[510] : *ZYNQ_VIP_INFO : FPGA Soft Reset called for 0x1
[510] : *ZYNQ_VIP_INFO : FPGA Soft Reset called for 0x0
[510] : M_AXI_GP0 : *ZYNQ_VIP_INFO : Starting Address(0x41200000) -> AXI Write -> 4 bytes
wr_id called with wr_size f0
510ID1 in strb task is ab1
run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 363.547 ; gain = 0.000
xsim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 363.547 ; gain = 32.008
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:01:35 . Memory (MB): peak = 363.547 ; gain = 47.297

----------------------------------------------

The problem is that after the first inst.write_data, the simulation seems to be stopped, and the rest code will not be executed.

I put the whole simulation log in the attachment.

Is there any advice how to fix this issue?

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Accepted Solutions
florentw
Moderator
Moderator
281 Views
Registered: ‎11-09-2015

Hi @mtang 

As per ds940, write_data is a blocking task which returns only after receiving BRESP from the slave

florentw_0-1620380072561.png

So you might want to check why the slave is not sending a BRESP in the waveform

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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2 Replies
florentw
Moderator
Moderator
282 Views
Registered: ‎11-09-2015

Hi @mtang 

As per ds940, write_data is a blocking task which returns only after receiving BRESP from the slave

florentw_0-1620380072561.png

So you might want to check why the slave is not sending a BRESP in the waveform

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

mtang
Visitor
Visitor
193 Views
Registered: ‎09-21-2019

Hi @florentw 

Thanks for the reply and hint, after check the simulation wave, found the fclk_reset0_n is kept active when issuing the axi write.

after fixing that, the simulation can be finished.

Regards.

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