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Participant
Participant
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Registered: ‎07-05-2017

Simultaneous FIFO read-write with Independent RD and WR clocks and different width related latency and fix required

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Hi

I'm want to use FIFO with simultaneous read and write options. I'm using Artix7 FPGA. My input is continuous, coming with 13.5MHz clock (WR clock) with 16 bit wide.  I have assigned FIFO depth of 2048. I'm reading from FIFO using MIG generated ui_clk, ie RD clk = MIG ui_clk. Both MIG sysclk and refclk is 200MHz. ui_clk (RD_clk) comes around 100MHz. My read width is 128bits. So total 256 times i may read the FIFO before it gets empty.

In the above case, what are the steps need to taken to make FIFO work properly. Is it OK to read and write at the same time as per above.

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi@bivin,

As mentioned in the user guide , the below equations should met to avoid the Simultaneous assertion of Full and Empty flag

(As clocks are different there are delays in assertion/deassertion of the FUll and empty flag due to the cross clock domain logic)

 

A) Time it takes to update full flag due to read operation < time it takes to empty a full FIFO

B) Time it takes to update empty flag due to write operation < time it takes to fill an empty FIFO

 

The left side equations in both the formula gives the latency of full flag updating  and empty flag updating respectively 

 

The latency formulas as below

 

 Capture1.PNG

 

        Capture2.PNG

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Moderator
Moderator
2,060 Views
Registered: ‎08-08-2017

Hi @bivin

 

I presume the FIFO implementation is independent clock block RAM.

it is absolutely fine to write and read simultaneously.

 

Have you tried to customize the FIFO generator with this configuration.  I have tried it in FIFO generator 13.2 and it is not allowing 

configuration as you mentioned.

 

Capture.PNG

 

Let us know the Wizard settings and try to simulation.

-------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and Accepts as Solution if you get one

--------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
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Participant
Participant
2,042 Views
Registered: ‎07-05-2017

Below are the settings screen-shot.

Capture1.JPG

Capture2.JPG

 

So with above specs, what could be the latency to read/write data ? What is the "Simultaneous Assertion of Full and Empty Flag" in page 153 of pg057 ? Will this be affected in above case? What will happen in case where my input is 128bit with ui_clk (WR_clk) and output is 16bit with 13.5MHz (RD_clk)? (Programmable full/empty signals are not getting updated after read/write is performed)

 

 

 

 

 

 

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Highlighted
Moderator
Moderator
2,001 Views
Registered: ‎08-08-2017

Hi@bivin,

As mentioned in the user guide , the below equations should met to avoid the Simultaneous assertion of Full and Empty flag

(As clocks are different there are delays in assertion/deassertion of the FUll and empty flag due to the cross clock domain logic)

 

A) Time it takes to update full flag due to read operation < time it takes to empty a full FIFO

B) Time it takes to update empty flag due to write operation < time it takes to fill an empty FIFO

 

The left side equations in both the formula gives the latency of full flag updating  and empty flag updating respectively 

 

The latency formulas as below

 

 Capture1.PNG

 

        Capture2.PNG

---------------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and Accepts as Solution

--------------------------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos