10-22-2013 06:01 PM
I have been using Coregen FIFO generator to generate a FIFO for my Spartan 3E platform.
I am not sure why the "Empy" signal doesn't behave as expected ?!
For example, if you look at the following snap shot, you will see that "empty" signal is de-asserted, when there is about three data word in the FIFO.
Isn't it that "empty" signal normally is deasserted right after there is one word in the FIFO? Why does it take for the FIFO to store about 3 words, before reporting that it is not empty?
By the way, in the generation of this core, I used independent read/write clock, but for the purpose of the simulation, read/write clocks are both tied to the same clock.
10-24-2013 11:52 PM - edited 10-24-2013 11:53 PM
maybe it's just the latency of the Empty flag.
Can you run a simulation where you only write one dataword to the fifo.
Then you should be able to see the Empty flag being deasserted as well and determine the latency that way.
This information should also be available from the FIFO IPs datasheet, but you might have to look for it thoroughly to find it.
Have a nice simulation
10-25-2013 09:53 AM
Just to eloborate If write and read clocks are not the same I think you aware there is a concept of CDC that comes into picture.
Empty flag will be generated in read clock domain comparing write and read pointers.
But these pointers will be transferred from one clock domain to another using double buffers and then sampled.
Hence I believe 3 clocks is expected.
even though you used write and read clocks teh same to keep things simple the same concept applies.
Also please see Table 3-20 through 3-25 of below pdf for latency figures for different modes
Hope this clarifies.
10-30-2013 01:31 AM