I have a design with two clock domains, a 62.5MHz Microblaze AXI subsystem, and a 28.8MHz digital radio subsystem. Four FIFO_DUALCLOCK_MACROs bridge the two subsystems, each hand wrapped with an AXI stream interface in Verilog using X_INTERFACE_INFO directives.
The .RST port for these four FIFO's, which comes through the 62.5MHz AXI interface from a Processor System Reset block, is giving me timing slack errors.
So my question is, what is best practice to reset a FIFO_DUALCLOCK_MACRO? Should I synchronize reset through one of the clocks? If so, which one?