01-05-2021 02:37 PM
I am coming to my wits end with this simulation. The picture below is the simulation of fifo in my design. See the delay between the rd_en and the data output. From the FIFO product guide, there should be 1 clock delay when reading a synchronous fifo.
I simulated the example design in Vivado and it seems to behave. Not sure what I need to do to get the simulation in Questasim to work.
01-08-2021 08:00 AM
Can you share your .XCI for your FIFO and I will use the Example design to simulate to see if I can reproduce the issue?
Is the behaviour consistent when you simulate with Vivado?
Is the simulation a Behavourial Simulation? Or a Post Synthesis/Implementation Functional/Timing Simulation?
01-08-2021 02:19 PM
Hi @sandrao ,
I am not able to attach the file. The forum web app removes it. Can you please send me an alternate way to provide it to you?
I should mention that I simulated using Questasim the example from that xci file and that looked ok. I did notice, that the control signals are delayed by roughly 1/4th the clock period from the rising clock edge. I do not have this delay in my functional rtl sim. I cannot imagine having the need for it since I am not doing timing annotated gate level sim.
01-11-2021 04:04 AM
If I understand this correctly when you simulate with the Example Design the FIFO behavior is as expected in Questasim.
However when you use your own tb the behavior changes and it is not expected.
Is that correct?
When you simulation your tb in Vivado what is the behavior?
What are the differences between the Example Design TB and your?
I might move the question to the simulation board as it seems more like a simulation than IP question.
01-22-2021 11:47 AM
Yes! The example design simulates. The difference between my tb and example design, is that in case of example design, there is a delay between clock edge and control signals being driven by it, such as write enable and read enable, etc. Not sure, why that is delay is needed. Generally, in functional RTL sim, this should not matter.
I do not have that delay between active clock edge and control signals being driven by it. This is the only obvious difference between my tb and the example design. There cannot be much, it is a synchrnous fifo. It only needs, clock, data and enables.
01-24-2021 02:47 AM
Can you provide the .xci file and your tb so I can reproduce the issue?
02-02-2021 09:22 AM
My testbench is part of a larger simulation that will be complicated to share here. I had attached the picture of what I am seeing in my original post. You can see it here at the top of the thread.
I cannot attach the .xci file to this thread because of the error that I earlier reported to you and Samir at Avnet. Here it is again -
02-02-2021 09:56 AM
You may be seeing delta cycle problems in your simulation. One reason to put those small delays in is to make it unambiguous to the simulator which signal happens first, the clock edge, or the enable. Otherwise, if it isn't obvious from the test bench code, the simulator may not see the enable signal on the clock edge that you think it should.
02-03-2021 08:27 AM
Yes! that could be but I'm scratching my head as to where - everything points to the FIFO IP. If you look at the picture at the head of the thread. You will how the number of clocks after which the usedw goes after wr_en to the fifo is asserted.
I replaced the sync fifo with my own logic and I don't have that problem.
02-03-2021 09:32 AM
if you have not already, might be worth checking those warnings
wonder if you have any things like sensitivity list warnings or latches