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Registered: ‎08-06-2017

The bit width of rx_data_out and tx_data_out of an AXI-chip2chip

c2c.PNG

捕获.PNG

What factors will affect the bit width of rx_data_out and tx_data_out in the AXI-chip2chip.

As shown in the picture(and the clock frequency of axi_c2c_selio_rx_clk_in/axi_c2c_selio_tx_clk_in is 125MHz), I have a problem, sometimes the  bit width of rx_data_out and tx_data_out in the AXI-chip2chip is 14bit, and sometimes the  bit width of rx_data_out and tx_data_out in the AXI-chip2chip is 13bit, why?  So, I don't know the  bit width of rx_data_out and tx_data_out in the AXI-chip2chip how to change.

 

What is the change rule of the  bit width of rx_data_out and tx_data_out in the AXI-chip2chip?

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