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Qiao_Jin
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Registered: ‎05-23-2021

The difference of two ways to use BRAM

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Hi,

As I know, there are two ways to use BRAM in a design. One is using IP core Block Memory Generator and another is coding it. A coding example is showed below which is generating S-Box in AES.

Qiao_Jin_0-1627457986379.png

I am clear that BRAM can be generated using IP core. My question is how BRAM is generated by the second way. And can you tell me the difference between these two ways? If anyone can help I will appreciate a lot.

Sincerely yours

Qiao

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seamusbleu
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Registered: ‎08-12-2008

@dgisselqI guess I just think of LUTRAM as ROM as basically equivalent to LUT logic, but thinking about it some more, you are correct - as just LUT logic, it could fit into any CLB, and (in latest Xilinx familes) only half CLB's have LUTRAM.  But once again, if you just describe the logic, the synthesizer can choose how to implement it.

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seamusbleu
Voyager
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Registered: ‎08-12-2008

What you've done is describe a bunch of constants, not a BRAM.  If you want to infer a BRAM, I suggest you look at the coding examples available in Vivado.

Go to Tools->Language Templates->VHDL->Synthesis Constructs->Coding Examples->RAM->BlockRAM.

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Qiao_Jin
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Registered: ‎05-23-2021

Thank you for your reply. It is helpful. From there I saw the sentence If the chosen width and depth values are low, Synthesis will infer Distributed RAM. Does it mean that the example code just describes the behaviour of a block RAM and Synthesis will decide whether BRAM is used and how BRAM is used? The whole code of the above picture is showed below. It doesn't fit the example but BRAM is generated. Does it mean that there is a relatively large degree of freedom for Synthesis?

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Qiao_Jin
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Qiao_Jin_0-1627479995620.pngQiao_Jin_1-1627480041678.png

 

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seamusbleu
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Registered: ‎08-12-2008

If you described, say, a 32-deep RAM/ROM, then likely synthesis would put that in LUTRAM since it would be efficient.  If you want to specify it to use BRAM, you can add the attribute

attribute RAM_STYLE of ram : signal is "block"; -- "or distributed"

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dgisselq
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Registered: ‎05-21-2015

@seamusbleu ,

I don't get it.  Why would you want to use BRAM for an SBOX?

An S-Box is a 256-entry lookup table of, in this case, 8-bits.  On 7-series architectures, that can be implemented without RAM of any type.  It's just a lookup table.  Four LUT6's, together with a MUX8 and a FF, and you can build one bit of this S-Box.  32 LUT6's and you've built your entire table.

LUTs are cheap.  BRAMs are expensive.  Why would you want to implement a lookup table in BRAM?

That's problem #1.

Problem #2 is that BRAM outputs typically don't have resets.  That means that your logic above, if (RESET) V <= 1; else V <= ramtable(index); might not map into block RAM.  V <= ramtable(index); would map nicely, but the reset would require extra logic.  If the reset is important to you, you might need to be aware that not all architectures support resets when reading from block RAMs.  I'm not sure whether or not yours does.

Dan

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seamusbleu
Voyager
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Registered: ‎08-12-2008

@dgisselq- I am just responding here, the above is not my code. 

Depending upon your design and part selection, you may want to use BRAM or LUTs - it's hard to say which is "expensive".  So I gather an S-Box is 256x8 = 1Kb of ROM.  Agreed that it would fit in 32 LUTRAM's, so that's pretty efficient.  All I was pointing out to the above question is that the synthesizer might choose to put that in distributed or block ram, but you can tell it which you want.  As to the reset question, a bram does have a reset on it's output, so it can be handled by the above code, though I wouldn't say for sure it would be properly inferred without testing it or looking into it more closely than I will now.

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luzhandr
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Registered: ‎05-10-2019

those are not  only ways to produce BRAMs.

You could also use XPMs, Unimacros or directly instantiate the BRAM primitive, although this last one rarely makes sense.

See UG953 or UG974 depending on device you are using.

dgisselq
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Registered: ‎05-21-2015

@seamusbleu ,

> I am just responding here

Oops.  My bad.  I should've tagged @Qiao_Jin , Sorry.

> If you described, say, a 32-deep RAM/ROM, then likely synthesis would put that in LUTRAM since it would be efficient

If the table is fixed, why would you need a LUTRAM over any other LUT architecture?  Fixed tables fit into LUTs nicely without the need for LUTRAMs.

Dan

seamusbleu
Voyager
Voyager
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Registered: ‎08-12-2008

@dgisselqI guess I just think of LUTRAM as ROM as basically equivalent to LUT logic, but thinking about it some more, you are correct - as just LUT logic, it could fit into any CLB, and (in latest Xilinx familes) only half CLB's have LUTRAM.  But once again, if you just describe the logic, the synthesizer can choose how to implement it.

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Qiao_Jin
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Registered: ‎05-23-2021

@seamusbleu Thank you for your apply. I need some time to understand  the details but I have known that Synthesis has its rule when the code is not so specific.

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Qiao_Jin
Observer
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Registered: ‎05-23-2021

@dgisselq Thank you for your reply. There are some scenes to use BRAM for S-box. For example, BRAM is resistant to side-channel attacks. I am investigating the security implications of BRAM so it may not fit some efficient scenes.

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Qiao_Jin
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Registered: ‎05-23-2021

@seamusbleu Thank for your reply again. Sorry for my typing error before.

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Qiao_Jin
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@luzhandr Thank you for your reply. I will check the files you mentioned.

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luzhandr
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Registered: ‎05-10-2019

@seamusbleu 

Your description of LUTRAM is inaccurate. Every LUT has 64 RAM cells inside. that's how they work: there are up to 6 inputs pro LUT with 2^6=64 possible combinations. And the RAM stores the output value for each combination. But not every LUT can be used as memory. In 7 Series a third of LUTs can be used (externally accessible) RAM (according to the CLB Guide). That what makes difference between SLICEM (Memory) und SLICEL (Logic) slices.

perhaps it is a language issue

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luzhandr
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Registered: ‎05-10-2019

@Qiao_Jin 

Also look p. 61 in UG949 ("Inferring RAM and ROM")

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Qiao_Jin
Observer
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Registered: ‎05-23-2021

Oh, thanks for your information.

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