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zhanglihua
Observer
Observer
9,393 Views
Registered: ‎03-09-2014

The read data from RAM is not the same as the write data

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Hi,

I have a issue when I use dual port RAM.

The write data is from the ddr2 RAM's rd_data_fifo, when writing, the data of douta is the same as the data of dina and rd_data_rise, the data of doutb is similar. While when reading, the read data is not the same as the write data. A few of lower bits is x ,not 0 or 1.When the radix is set to hex in modelsim, the lower 2 or three is x. While when the read data is used in add IP core, the result can be computed, and the lower bits of add result is x. It's so strange.

The first picture is the write data, the second picture is the read data, and the third data is the least 16 bits of douta.

Thanks.

Zhanglihua.

01.jpg
02.jpg
03.jpg
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criley
Xilinx Employee
Xilinx Employee
15,458 Views
Registered: ‎08-16-2007

Do you have REORDERING on? Is it set to STRICT or NORM (default)? It's probably the memory controller reordering your data to improve throughput. Do you see incorrect read data on the user interface?

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criley
Xilinx Employee
Xilinx Employee
15,459 Views
Registered: ‎08-16-2007

Do you have REORDERING on? Is it set to STRICT or NORM (default)? It's probably the memory controller reordering your data to improve throughput. Do you see incorrect read data on the user interface?

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zhanglihua
Observer
Observer
9,342 Views
Registered: ‎03-09-2014

Hi,

criley,

I have solved the issue. I defined another dual port RAM, ram18, I copied the RAM ip core in module, changed the IP's name ,but forgot to change the port name, and the width of the dout in the ram18 is 10, not 64, so the dout had two originals.

It seems that I can't find the REORDERING in dual port RAM when generate the RAM ip core. Maybe you talked about the ddr2 RAM. I refered it to tell the source of the wirte data.

Thank you so much.

Regards,

Zhanglihua.

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