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Visitor
Visitor
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Registered: ‎09-18-2020

Trouble debugging JESD core

I am having some issues debugging the JESD core and was hoping for some advice.  I am using a Kintex-7 with an AD9172 DAC attached to it (both are eval boards).  The lanes between them appear to be configured properly and I can setup the AD part over their ACE software.  I am attempting to read out a simple tone from BRAM and output it over the DAC.  I was not getting the results I expected so I started to debug it, but am a little confused at what I am looking at.  I am using a block design and have connected the system ILA to the gtx output lines to monitor it.

garengllc2_0-1606230618979.png

The data I am sending is 16b I/Q data in this format:

I0=0x4000 i1=0x2D41 I2=0x0000 I3=0xD2BF
Q0=0x0000 Q1=2D41 Q2=4000 Q3=2D41
(and repeat)

Looking at the AD9172 data sheet, Mode 9 (LMFS=4222) should be setup like this:

garengllc2_1-1606230946110.png

If I look at the ILA output of what is transmitting, it looks like this:

garengllc2_2-1606231636951.png

Looking at the Lanes (which are ordered from 0->3), the data looks to me like it is lined up as it should be based on the table in the image above it.  Yet when I look on a spectrum analyzer, this spectrum looks like junk (I should see a tone at LO+150MHz).  What can I do in the cores to help debug this problem?

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Participant
Participant
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Registered: ‎05-24-2020

@garengllc2 

Did you go verify the data mapping based on PG150 page 100 

raj_0-1607028241940.png

Did you configure the DAC part based on the configuration you desire, eg - data format of the DAC binary or twos complement 

 

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