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vhdlveri123
Explorer
Explorer
335 Views
Registered: ‎04-21-2021

Two GT in same quads or different quads

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Hi,

I would like to connect two Aurora IPs. I am confused whether to use the GTHs from same quad or from different quads. And if its same quad, what about GT_COMMON and should i generate the example design?

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kdeshwal
Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎11-12-2019

Hi @vhdlveri123 ,

If I am understanding it correct, you want to use 2 Aurora IP on one device, isn't it?
If yes, then it completely depends on you or to be precise on your device's resources to use same quad or different.
If there is limitation to quad and you are required to share 1 quad to 2 Aurora protocols then go for quad sharing.
But my recommendation would be, if possible, do not go for quad sharing.

If you want to share quad, then you need to take care of the common block as both the IP instantiation will target the same physical resource (common block).
To overcome this, configure one Aurora IP core as "Include Shared Logic in Core" and the other as "Include Shared Logic in Example Design".
Now the 1st one will act as master and the other one slave.
GTREFCLK will be provided by master (which contains common block) to slave.

Refer Shared Logic Section in PG074 pg67.
Also check out Figure 3-17: Shareable Resource Connection Example Using IP Integrator in the same section.

Thanks,
Kuldeep
 

Thanks,
Kuldeep

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1 Reply
kdeshwal
Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎11-12-2019

Hi @vhdlveri123 ,

If I am understanding it correct, you want to use 2 Aurora IP on one device, isn't it?
If yes, then it completely depends on you or to be precise on your device's resources to use same quad or different.
If there is limitation to quad and you are required to share 1 quad to 2 Aurora protocols then go for quad sharing.
But my recommendation would be, if possible, do not go for quad sharing.

If you want to share quad, then you need to take care of the common block as both the IP instantiation will target the same physical resource (common block).
To overcome this, configure one Aurora IP core as "Include Shared Logic in Core" and the other as "Include Shared Logic in Example Design".
Now the 1st one will act as master and the other one slave.
GTREFCLK will be provided by master (which contains common block) to slave.

Refer Shared Logic Section in PG074 pg67.
Also check out Figure 3-17: Shareable Resource Connection Example Using IP Integrator in the same section.

Thanks,
Kuldeep
 

Thanks,
Kuldeep

-------------------------------------------------------------------------------------------------------------
Please give Kudo and Accept as a Solution if solution provided seems helpful.
Have a look at our Versal Design Process Hub, Versal Blogs and the Versal Forum Useful Resources
-------------------------------------------------------------------------------------------------------------

View solution in original post