UG573 (v1.9) indicates on p.104 regarding the UltraRAM RST_ inputs that "In synchronous reset mode, which is the default, all output flip-flops and latches are synchronously reset to “0”."
Clarification is needed, when the OREG_A and OREG_ECC_A (or OREG_B and OREG_ECC_B) attributes are set to false so that read data is being produced asynchronously, that the above-cited reset behavior (e.g., data outputs being forced low) does in fact occur, given that no output flipflops or latches are in the picture (per Fig. 2-3 on p.97).
