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Explorer
Explorer
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Registered: ‎07-10-2013

UltraRAM Reset Behavior

UG573 (v1.9) indicates on p.104 regarding the UltraRAM RST_ inputs that "In synchronous reset mode, which is the default, all output flip-flops and latches are synchronously reset to “0”."

Clarification is needed, when the OREG_A and OREG_ECC_A (or OREG_B and OREG_ECC_B) attributes are set to false so that read data is being produced asynchronously, that the above-cited reset behavior (e.g., data outputs being forced low) does in fact occur, given that no output flipflops or latches are in the picture (per Fig. 2-3 on p.97).

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Contributor
Contributor
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Registered: ‎05-27-2008

Good question!

If OREG_ attributes are set to false, what effect do the RST_ inputs have? Is the data output unknown or based on the last access? 

jd
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