cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
basti2357
Visitor
Visitor
489 Views
Registered: ‎02-12-2020

Ultrascale+ GTY Aurora64b66b 4-Lane 100G PCS loopback gt_pll_lock triggering

Hi,

I'm testing Aurora64b66b as 4-Lane Configuration on Ultrascale+ GTY Transceivers at maximum line rate.

For simulation everything works well. When implementing the design on a ZU28DR gt_pll_lock, rx_fsm_resetdone, tx_fsm_resetdone, and link_reset toggle. This occurs for both PCS loopback using one core and normal operation with two cores connected using a QSFP-DAC.

-User clock is generated
-qplllock stays high
-rx_bufstatus is 3'd0 for each lane

The core is configured as Duplex, 4-Lane, INIT CLK is 100MHz and GT_Ref is 161.1331MHz both generated from an Ultra Low Jitter Clock Generator on the PCB.

Thanks in advance,

basti2357 

0 Kudos
1 Reply
rkhatri
Moderator
Moderator
351 Views
Registered: ‎01-10-2019

Hi @basti2357 ,

This AR may be helpful here to debug the Reset issue.

https://www.xilinx.com/support/answers/59435.html

Thanks,
Rahul Khatri
---------------------------------------------------------------------------------
Please Kudo or Accept as a solution, If this Post helped you.
---------------------------------------------------------------------------------
0 Kudos