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Explorer
Explorer
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Registered: ‎05-16-2014

VHDL AXI Master to initialize JESD TX & RX

I have a JESD Tx and JESD Rx. I would like to initialize these two IP's. Is there any VHDL that can do this? I think it's an AXI Master.

Can the AXI Read/Write simulation Procedures from the example design be used?

 

thanks,

swimteam

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