Presently working on Redpitaya ZYNQ board.. my work is related to Stream ADC IP. And I wanted to add an extra register with padding (Inshort i want pass dummy bit). So I just edit Verilog code for Stream ADC IP, but somehow it's not showing expected output, infect it comes with minus value... and every time output is (-1). ... Here I attached my Verilog file and output.
Pls have a look and suggest me where is my mistake!! ADC output