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Contributor
Contributor
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Registered: ‎08-11-2019

Verilog code for ADC

Hii, everyone

Presently working on Redpitaya ZYNQ board.. my work is related to Stream ADC IP. And I wanted to add an extra register with padding (Inshort i want pass dummy bit). So I just edit Verilog code for Stream ADC IP, but somehow it's not showing expected output, infect it comes with minus value... and every time output is (-1). ... Here I attached my Verilog file and output. 

Pls have a look and suggest me where is my mistake!!  ADC outputADC output

PS: I already tried with removing MSB bit value.

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Scholar
Scholar
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Registered: ‎05-21-2015

Check your clock and make sure it is running.

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