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kadirakin85
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12,631 Views
Registered: ‎10-16-2010

Verilog file generation for the simulation of BRAM using Vivado

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Hello,

I have a small problem for Vivado 2015.4. I have generated BRAM using IP Catalog of Vivado. I have selected Verilog as the target language in Project Settings. Simulator language is selected as verilog for Simulation Settings. I want to simulate BRAM using Modelsim (behavioral simulation). When I look at the sim folder (.ip_user_files\ip\myBRAM\sim), I see only vhd file. Xilinx ISE was generating verilog file too but Vivado did not generate. How can I generate verilog file of BRAM to be used in simulation in Modelsim using Vivado ?

 

 

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vemulad
Xilinx Employee
Xilinx Employee
23,274 Views
Registered: ‎09-20-2012

Hi @kadirakin85

 

I understand that you are looking for verilog simulation model of BMG IP.

 

With Vivado 2015.3, 2015.4 we deliver only VHDL simulation model with BMG IP.

 

We are planning to deliver verilog simulation model for BMG IP in our next release vivado 2016.1.

 

Hope this info helps.

Thanks,
Deepika.
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arpansur
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Registered: ‎07-01-2015

Hi @kadirakin85,

 

To simulate using Modelsim you can use following command in Tcl console

export_simulation

 

The above command will generate the script for simulation in supported 3rd party simulator. So it will contain a folder for modelsim also.

 

Thanks,
Arpan

Thanks,
Arpan
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kadirakin85
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Registered: ‎10-16-2010

Thank you very much, but I am not sure if this is what I need. Do I have to make simulation using Vivado to be able to export ? I tried export_simulation but it tries to export all the design and it asks update of many unrelated IPs. Vivado even asks to me to update microblaze although it is up-to-date and I will not simulate microblaze, so this can be question of another topic. Indeed, I am not trying to simulate all the design, I want to simulate only BRAM that I use in my design using Modelsim. If somehow I will make export_simulation function working, will it also generate me verilog file of BRAM for simulation ? 

I thought there is an easy way to ask Vivado to generate verilog file of BRAM for the simulation (this was done automatically by ISE when BRAM is generated at first time), but Vivado only generates VHD file for the simulation. 

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arpansur
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Registered: ‎07-01-2015

Hi @kadirakin85,

 

You can set "top module" in simulation as .vhd file for BRAM.

No it won't create verilog simulation file. But it will write scripts to simulate the design using modelsim.

 

Just out of curiousity:

Why are you looking for verilog simulation file?

 

Thanks,
Arpan

Thanks,
Arpan
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kadirakin85
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Registered: ‎10-16-2010

Because I am good at verilog but not in vhd :) If everytime Xilinx ISE tools ask for preference of the people for verilog or vhd, the reason is answering the preference of people, am I right :) but for this case it did not ask for the preference unfortunately :)

Anyway, if there is no easy solution for this question, I will use vhd files for the simulation.. 

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vemulad
Xilinx Employee
Xilinx Employee
23,275 Views
Registered: ‎09-20-2012

Hi @kadirakin85

 

I understand that you are looking for verilog simulation model of BMG IP.

 

With Vivado 2015.3, 2015.4 we deliver only VHDL simulation model with BMG IP.

 

We are planning to deliver verilog simulation model for BMG IP in our next release vivado 2016.1.

 

Hope this info helps.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi @kadirakin85

 

Is your query answered?

Thanks,
Deepika.
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kadirakin85
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Registered: ‎10-16-2010

Thanks, yes, I selected your answer as solution. So, I am waiting for 2016.1 :)

 

 

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siticompany
Adventurer
Adventurer
11,998 Views
Registered: ‎09-27-2010

If you generate your core in your project in a directory of the core will be file

<name_of_your_core>_sim_netlist.v

You can use it for simulation instead of the core.

Ilya
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