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Registered: ‎10-15-2019

Vivado 与VCS联合仿真Xilinx IP核工程

vivado版本是2015.1,VCS版本是2014.3,下面是我的报错,有人可以解答一下吗?谢谢! //===========================error============================ Chronologic VCS (TM) Version I-2014.03_Full64 -- Mon Nov 25 08:57:03 2019 Copyright (c) 1991-2014 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Error-[SETUP_MAX_INC_LEVEL] Max level of include line exceeded Too many levels(8) of includes in line 'OTHERS=/home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/synopsys_sim.setup '. It should be less than 8. //======================================synopsys_sim.setup============================ 这个是synopsys_sim.setup文件的内容 OTHERS=/home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/synopsys_sim.setup xil_defaultlib : vcs/xil_defaultlib fifo_generator_v13_0_1 : vcs/fifo_generator_v13_0_1 secureip : /home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/secureip unisims_ver : /home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/unisims_ver unimacro_ver : /home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/unimacro_ver unifast_ver : /home1/quyl/ddr3_2015_vcs_sim_an430_ov5642/ddr3_2015_vcs_sim_an430_ov5642.cache/compile_simlib/unifast_ver
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