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dwisehart
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Registered: ‎06-23-2013

Vivado BRAM Independent Clock FIFO misbehaving in simulation

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I used the IP Catalog to generate an independent clock FIFO from BRAM where the write size is 64 bits with a depth of 512 and the read size is 8 bits with a depth of 4096.  I am not seeing my expected results.

 

The simulation shows several things:

  1. The write count grows by 1 each time 64 bits is written to the FIFO, but the read count grows by 8 every time 8 bits is read from the FIFO for the first 7 8-bit reads and then the read count freezes even though I read many more times from the FIFO.
  2. After seven or eight writes to the FIFO, the Empty and the Almost Empty flags go low.  Then, I start reading and even though I read many more times, the Empty and the Almost Empty flags never go high again.
  3. The data I write to the FIFO over eight cycles never shows up in the read output.

Have I misconfigured the FIFO somehow, or is it misbehaving?

 

Thanks,

Daniel

 

2013-07-06_03-32-21.png

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balkris
Xilinx Employee
Xilinx Employee
22,238 Views
Registered: ‎08-01-2008

This  seems bug with FIFO Generator IP and will fixed in 2013.3 release

 

Regards

Balkrishan

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
15,068 Views
Registered: ‎08-01-2008

Hi,

 

Can you please confirm if you have wrote your own FIFO code or you are using FIFO Generator code.

 

I am assuming you are using FIFO Generator core with  independent clock and BRAM as memory resource.

 

Can you please send me the complete xco file.

 

You need to make sure you are driving all the inputs correctly.

 

We have provided test bench with FIFO Generator core.

 

You can use provided test bench and see if you can reproduce the issue

 

 

Thanks and Regards
Balkrishan
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dwisehart
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Registered: ‎06-23-2013

I am using the FIFO generator.  The full source snapshot is attached to my posting.  I will also try the Test Bench.

 

Daniel

 

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balkris
Xilinx Employee
Xilinx Employee
15,047 Views
Registered: ‎08-01-2008

Hi,

 

It seems you have not derived input  signals correctly.  Please refer pg057 for detail example section and use provided test bench with the core.

 

You can also refer interface debug section and quick start example design.

 

 

There are few timing figure are given in datasheet you can see how the input signal are asserted and how the output signals responding  with input signal

 

For example

 

Write operation

 

Check fig 3.2  in PG057

 

Read operation

 

 

Check fig 3.3  in PG057

 

 

 

Hope it will help you

 

Thanks and Regards
Balkrishan
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dwisehart
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Registered: ‎06-23-2013

OK, so I took a look at the test bench, which is all in VHDL, even though I built my project in Verilog.  

 

The test bench does not even look at the counters, so it cannot be said to judge them as working or not working.

 

The test bench continues to write into the FIFO after it is full, so it cannot tell if the FIFO only works when it is overfilled or if it will work when it is partially filled.

 

The test bench fills up the FIFO with the same value over and over again, so it cannot tell if items are pulled out of the correct memory location in the correct order or not.

 

When I run the test bench it tells me it failed:

 

INFO: [Vivado 12-1390] *** Running xsim
with args "fifo_generator_64_8_tb_behav -key {Behavioral:sim_1:Functional:fifo_generator_64_8_tb} -tclbatch {fifo_generator_64_8_tb.tcl} -log {fifo_generator_64_8_tb_behav.log}"
Vivado Simulator 2013.2
Time resolution is 1 ps
WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.
Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
STATUS:
00
INFO: [Vivado 12-1395] XSim completed. Design snapshot 'fifo_generator_64_8_tb_behav' loaded.
launch_xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3956.531 ; gain = 14.117
run 200 us
STATUS:
80
Error: Data mismatch found
Failure: Simulation failed

I have attached a snapshot of the test bench.

 

Daniel

 

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balkris
Xilinx Employee
Xilinx Employee
14,902 Views
Registered: ‎08-01-2008

Can you please try on Modelsim Simulator. We have seen such behavior with  NCSIM

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
22,239 Views
Registered: ‎08-01-2008

This  seems bug with FIFO Generator IP and will fixed in 2013.3 release

 

Regards

Balkrishan

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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dwisehart
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Registered: ‎06-23-2013

Many thanks, Balkrishan.  

 

I will pick it up and test it when it is available.

 

Daniel

 

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debrajr
Moderator
Moderator
14,840 Views
Registered: ‎04-17-2011

Hello Daniel,

 

Thanks for your reply. As you would be trying the same in 2013.3, I would be marking the post from Bala as an Accepted Solution for others to refer in future.

 

Moving forward, if you have any post and you think that the reply from any user is helpful, you can mark it as an Accepted Solution.

 

We truely value your contribution towards making our tools more robust by highlighting various issues you face and please feel free to create new posts with new queries.

 

Best of luck!

Regards,
Debraj
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dwisehart
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Registered: ‎06-23-2013

Thanks for your feedback, but saying that someday I might get a solution is not what I would yet call an acceptable solution.  To be a solution it has to solve my problems.  What I have so far is a promise--which is good--but not yet a solution.

 

Regards,

Daniel