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arotenst
Explorer
Explorer
868 Views
Registered: ‎09-14-2018

Vivado complains that xlconcat input pins are connected to different type of pins

Hello,

I use 32-bit wide xlconcat block in BD. Vivado (2018.3) is complaining that xlconcat input pins are connected to different type of pins, which is not right. I thought that just replacing the xlconcat block fixed the problem (it did once), but later it turned out that it was not a solution. Any ideas why this is happening?

I have attached the snap shots of the error messages.  

Thank you.

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ashishd
Xilinx Employee
Xilinx Employee
828 Views
Registered: ‎02-14-2014

Hi @arotenst ,

You can confirm if there is really mismatch using below command (Assuming name of Concat bd cell is xlconcat_0) -

get_property TYPE [get_bd_pins -filter {DIR == I} /xlconcat_0/*]

This will report TYPE of all input pins of xlconcat_0 BD cell. Compare this will TYPE of output pins (of other cells) which are connected to these inputs.

If this doesn't sort problem out and if you don't have any custom IPs or module references in your block design, then you can share output script after using command : write_bd_tcl -no_ip_version recreateBD.tcl

Regards,
Ashish
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arotenst
Explorer
Explorer
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Registered: ‎09-14-2018

Hello Ashish,

Thank you for your notes. A week ago I was able to "fix" it by just replacing the xlconcat (delete and add). That helped then. Now it does not work. Trying to find the troubling inputs I had to connect all of them to Constant. The error during design validation still persisted. It looks like a bug.

Anyway, I will follow your suggestions and update the post. May be tomorrow.

Thank you.   

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arotenst
Explorer
Explorer
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Registered: ‎09-14-2018

Hello Ashish,

I added a new xlconcat and make all connections. The result of

get_property TYPE [get_bd_pins -filter {DIR == I} /xlconcat_0/*]

is 32 undefs:

undef undef undef undef undef undef undef undef ...

What does that mean?

Thank you.

 

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arotenst
Explorer
Explorer
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Registered: ‎09-14-2018

One more thing. After running the command      get_property TYPE [get_bd_pins -filter {DIR == I} /xlconcat_0/*]

I noticed that the unused input pins (connected to Constant) become 32-bit wide. I have attached the snap shots. What is going on with Vivado?

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ashishd
Xilinx Employee
Xilinx Employee
799 Views
Registered: ‎02-14-2014

Hi @arotenst ,

It would be helpful if you can share output script generated using command mentioned in my earlier email (make sure there are no module references and custom IPs in your block design).

Regards,
Ashish
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arotenst
Explorer
Explorer
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Registered: ‎09-14-2018

I am not sure I understood. In my block design I have 3 big custom IPs. They have almost ten outputs total connected to different inputs of xlconcat. When I tried to debug I had a situation when I had just a single connection from Xilinx UART IP connected to xlconcat input, while the rest inputs were connected to Constant. 

Thank you. 

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ashishd
Xilinx Employee
Xilinx Employee
718 Views
Registered: ‎02-14-2014

Hi @arotenst ,

In that case even if you share the script, I won't be able to recreate block design unless I've repositories for 3 custom IPs. Better approach would be checking TYPE property of input pins of xlconcat IPs with TYPE property of output pins of custom IPs where connection is established. TYPE property can have values like clk, rst, undef based on pin type. 

If you want me to have a look at block design, then you've two options -

1. Share the repositories of your custom IPs along with script generated using command I mentioned earlier

2. Try reproducing the issue with only Xilinx IPs and then share the script generated using same command

Regards,
Ashish
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arotenst
Explorer
Explorer
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Registered: ‎09-14-2018

Hi Ashish,

I had the problem even when I replaced xlconcat and connect all inputs to the constant. It should not happen. I looks like a bug.

Anyway, I had to replace the Xilinx block with my custom IP. 

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ashishd
Xilinx Employee
Xilinx Employee
675 Views
Registered: ‎02-14-2014

Hi @arotenst ,

In order to debug it further and report it as a bug (if it really is), I need test design with which I should be able to recreate this issue.

It would be helpful if you can share it using either of methods stated in my earlier reply.

Regards,
Ashish
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